Improving and Optimizing Reliability in Future Technologies with High-κ dielectrics Barry P. Linder, E. Cartier, S. Krishnan, E. Wu IBM T. J. Watson Research Center Address Route 134, Room 06-258, Yorktown Heights, NY 10706 914-945-2478; e-mail: bplinder@us.ibm.com. ABSTRACT Three mechanisms primarily limit gate oxide scaling: bias temperature instability in both NFETs (PBTI) and PFETs (NBTI), and gate dielectric breakdown in NFETs (nTDDB). Strategies for reducing each mechanism are identified, and the overall effect of each mechanism on future scaling is discussed. Specialized ring oscillator structures that aid in the understanding of the effect of both PBTI and NBTI on circuit operation are explored. INTRODUCTION Over the past decade the gate stack in leading edge technology has migrated from Poly-Si and SiON to a metal gate with a bi-layer of a Hafnium based dielectric with a SiON interlayer (IL). This switch yielded immediate gains in gate leakage (I g ) and reliability, allowing a thinning of the inversion thickness (t inv ) from ~20Å to less than 14Å. Even though gate length scaling and performance would drive further thinning of the dielectric stack, reliability considerations limit this. Understanding the fundamental reliability mechanisms enables mitigation with process changes and an optimization of reliability, performance, and operating voltage (V max ). This paper will explore the main reliability mechanisms that are limiting scaling and the processes that improve reliability. Furthermore, the relationship between device level reliability and circuit reliability will be broached with ring oscillator data that shines light on the dominant reliability mechanism limiting V max . RELIABILITY MECHANISMS Dielectric breakdown (TDDB) and hot carrier injection (HCI) were the most studied degradation mechanisms in the 1990’s. Further scaling during the 2000’s mandated lowering the voltage and adding nitrogen to the SiO 2 . This decreased the relative importance of HCI while increasing the magnitude of PFET Bias Temperature Instability (NBTI). Switching to high-κ/metal gates generated a new reliability degradation mechanism, NFET Bias Temperature Instability (PBTI). Today, the main reliability mechanisms that limit further t inv scaling are bias temperature instability (BTI) for both NFETs (PBTI) and PFETs (NBTI), and NFET dielectric breakdown (nTDDB). PBTI is caused by bulk electron trapping at oxygen vacancies in the thick hafnium based dielectric top layer, while NBTI is the result of hole trapping in the SION IL and interface trap generation at the silicon interface. nTDDB is directly controlled by the dielectric layer thicknesses and the resulting gate leakage current density. Intensive research by a multitude of groups has revealed a multitude of approaches to reduce these mechanisms. PBTI Reducing the thickness of the high-κ layer is the primary means of controlling PBTI. Thinning the high- κ directly reduces the areal density of oxygen vacancies, which consequently decreases PBTI [1]. Figure 1 plots Ramp Voltage Stress (RVS) PBTI data for different HfO 2 thicknesses [2]. The plotted value is the ramp voltage at which the threshold voltage (V t ) shifted by 50 mV. There are clear gains with thinner HfO 2 which translate to lower PBTI. Both gate leakage constraints and film continuity limit the thinning of the high-κ film to approximately 15Å. Low power technologies may require even thicker high- κ layers, creating a trade-off of power consumption and PBTI. -5 -4 -3 -2 -1 0 1.50 1.55 1.60 1.65 1.70 1.75 1.80 1.85 1.90 1.95 2.00 Voltage to 50 mV dV t (V) HfO 2 Relative Thickness (Å) FIGURE 1. PBTI RVS data as a function of HfO 2 thickness. Thinner HfO 2 layers reduce PBTI, which translates to a higher RVS value. NBTI NBTI is a combination of both hole trapping within the IL and interface generation at the Silicon / IL interface. Decreasing the nitrogen in the IL or using a SiGe channel for PFETs reduces NBTI (Fig. 2) [3]. Nitrogen generates hole traps within the IL, directly increasing NBTI. Conversely reducing Nitrogen eliminates hole trapping sites. Creating a SiGe PFET channel raises the substrate valence band energy level, which consequently reduces the ability of inversion hole carriers to access hole traps within the IL [4]. nTDDB Gate tunneling current (I g ) is the primary cause of nTDDB, so processes that reduce I g will increase nTDDB reliability. I g may be reduced by thickening either the IL or the high-κ layer. Increasing the dielectric constant of either film would allow a thicker film without decreasing inversion capacitance. This would increase nTDDB while maintaining t inv and subsequently, performance. Figure 3a compiles Ramp Voltage Breakdown (V bd ) data for films with varying IL thicknesses and nitrogen content with an identical high-κ film, while Figure 5b compiles TDDB data for various high-κ and IL compositions and thicknesses. The increase in V bd and nTDDB with lower gate leakage follows a universal law independent of the mechanism for I g reduction. 978-1-4673-3082-4/13/$31.00 ©2013 IEEE