332 IEICE TRANS. ELECTRON., VOL.E93–C, NO.3 MARCH 2010 PAPER Special Section on Circuits and Design Techniques for Advanced Large Scale Integration Difficulty of Power Supply Voltage Scaling in Large Scale Subthreshold Logic Circuits Tadashi YASUFUKU †a) , Member, Taro NIIYAMA † , Zhe PIAO † , Nonmembers, Koichi ISHIDA † , Member, Masami MURAKATA †† , Nonmember, Makoto TAKAMIYA † , and Takayasu SAKURAI † , Members SUMMARY In order to explore the feasibility of large-scale subthresh- old logic circuits and to clarify the lower limit of supply voltage (V DD ) for logic circuits, the dependence of the minimum operating voltage (V DD min ) of CMOS logic gates on the number of stages, gate types and gate width is systematically measured with 90 nm CMOS ring oscillators (RO’s). The measured average V DD min of inverter RO’s increased from 90mV to 343 mV when the number of RO stages increased from 11 to 1 Mega, which indicates the difficulty of V DD scaling in large-scale subthreshold logic cir- cuits. The dependence of V DD min on the number of stages is calculated using the subthreshold current model with random threshold voltage (V TH ) variations and compared with the measured results, and the tendency of the measurement is confirmed. The effect of adaptive body bias control to compensate purely random V TH variation is also investigated. Such com- pensation would require impractical inverter-by-inverter adaptive body bias control. key words: minimum operating voltage, subthreshold, logic, variations, body bias 1. Introduction Very low-voltage operation of VLSI’s is effective in reduc- ing both dynamic and leakage power and the maximum en- ergy efficiency is achieved at low V DD (e.g., 320 mV [1]). Thus, many works have been carried out on the subthreshold operation of logic circuits [1]–[5] and SRAM’s [6], where V DD is less than V TH of transistors. However, the number of transistors in the previously reported subthreshold circuits is small (e.g. 70 k transistor logic circuits at V DD of 230 mV [1], a 32 kbit SRAM at V DD of 160 mV [6], and a 1000-stage inverter chain at V DD of 60 mV [4]), and the possibility of mega-gate-scale subthreshold circuits is not clear. V DD min is the minimum power supply voltage when the circuits operate without functional errors. RO’s are useful V DD min detectors [7], because RO’s stop oscillation when the first functional error in the logic circuits arises. Fig- ure 1 shows the simulated waveform of the 5-stage CMOS inverter RO. V DD is varied from 0.2 V to 0V. At V DD min of 50mV, RO stops oscillating. In order to emulate the recent SoC’s, mega-stage-scale RO’s are required, because the re- cent SoC’s have 10–100Mega logic gates. With technology scaling and an increased number of transistors on a chip, Manuscript received July 12, 2009. Manuscript revised October 2, 2009. † The authors are with The University of Tokyo, Tokyo, 153- 8505 Japan. †† The author is with Semiconductor Technology Academic Re- search Center (STARC), Yokohama-shi, 220-0033 Japan. a) E-mail: tdsh@iis.u-tokyo.ac.jp DOI: 10.1587/transele.E93.C.332 Fig. 1 Simulated waveform of 5-stage CMOS inverter RO. Definition of V DD min is shown. V DD min will increase, because the more gates there are, the more likely it is that the worst-case condition will occur, and thus a higher V DD will be required. However, the systematic measurements of V DD min of the subthreshold logic circuits made with scaled devices have not yet been reported. Systematically measured dependence of V DD min of CMOS logic gates on the number of stages, gate types and gate widths with 90nm CMOS RO’s are reported for the first time, in order to explore the feasibility of large-scale- subthreshold logic circuits and to clarify the lower limit of V DD for logic circuits [7], [8]. In Sect.2, the design of CMOS RO’s for V DD min mea- surement and the measured V DD min is presented. Section 3 presents the analysis of the origin of V DD min with SPICE and MATLAB to explain the measured results. Section 4 presents the fine-grain adaptive body bias control to reduce V DD min . 2. Measured V DD min of 90 nm CMOS RO’s 2.1 Design of CMOS RO’s for V DD min Measurement Figure 2 shows a schematic of the proposed RO circuits to enable V DD min measurement. The output of RO should be amplified, because the output amplitude of the RO is small Copyright c  2010 The Institute of Electronics, Information and Communication Engineers