Offset voltage of Schottky-collector silicon-on-glass vertical PNP’s G. Lorito, L. K. Nanver and N. Nenadović Laboratory of ECTM, DIMES, Delft University of Technology, P.O. Box 5053, 2600 GB Delft, The Netherlands, Email: nanver@dimes.tudelft.nl Abstract — Silicon-on-glass vertical PNP’s are fabricated and investigated with respect to the influence of the collector design on the offset voltage. With Schottky collector contacts the offset voltage can be made both very low (< 0.1 V) or very high (~ 0.3 V). Index Terms — Offset voltage, ohmic collector contact, Schottky collector contacts, silicon-on-glass, vertical PNP’s. I. INTRODUCTION Substrate transfer processes are attracting attention as possible low-cost technologies enabling high-performance low-power RF integrated circuits with on-chip RF integration of active devices and high-quality passive components [1, 2]. From a device design point of view they are very attractive if, like the silicon-on-glass process used in this work [3], they give direct access to both sides of the device. Particularly for bipolar transistors, where the active current path is vertical to the surface from the emitter to the collector, the availability of the collector contact directly under the emitter can eliminate the need for buried layers, the device size can be considerably reduced and the speed performance increased by the reduction of parasitic series resistance and capacitance. In this work fully-implanted vertical PNP’s (VPNP’s) have been added to a 25 GHz silicon-on-glass NPN process [3]. Several types of collector contact designs, including ohmic p + -regions and p- or n-type Al/Si Schottky junctions, were fabricated on the backside of the wafer to create different p-type BJT’s. Designs similar to the n-Schottky collector device have in the past been proposed and predicted to give potentially better BJT speed performance due to the low collector resistance, transit time and storage time [4]. The possible speed advantage cannot be verified with the present devices because the relaxed device dimensions result in a large base transit time that dominates the device speed. An advantage of the dimensions, however, is that the low current I-V characteristics are near ideal and the influence of the collector design on the offset voltage can be accurately investigated. For high-frequency applications the offset voltage is normally not an issue but in analog/power applications it can lead to undesirable extra power consumption and must be taken into consideration. Fig. 1. SIMS profile of the intrinsic VPNP implantations after the 950°C thermal anneal. The distance to the collector contact is indicated for the three fabricated values of the silicon top-layer thickness: 640, 740 and 940 nm. Fig. 2. Schematic cross section of the silicon-on-glass p-type BJT with (a) implanted and laser-annealed ohmic collector contact, (b) p-Schottky collector contact and (c) n-Schottky collector contact. Depletion regions are indicated by white regions in (a)-(c). II. EXPERIMENTAL MATERIAL The doping profile of the intrinsic VPNP is shown in Fig. 1. A number of collector designs were realized by varying both the thickness, t Si , and doping of the SOI silicon top-layer as well as the collector contacting method. Schematic cross sections of the fabricated devices are given in Fig. 2. Ohmic contacts (Fig. 2a) were made by a 5 × 10 15 cm -2 5 keV BF 2 + implantation and dopant 22 0-7803-9309-0/05/$20.00 ©2005 IEEE IEEE BCTM 2.2