PureGaB p + n Ge diodes grown in large windows to Si with a sub-300 nm transition region Amir Sammak ⇑ , Lin Qi, Wiebe B. de Boer, Lis K. Nanver ECTM-DIMES, Delft University of Technology, Feldmannweg 17, 2628 CT Delft, The Netherlands article info Article history: Available online 12 May 2012 Keywords: Ge-on-Si Epitaxial growth Chemical vapor deposition Ge diodes PureGaB Ultrashallow junctions abstract Ultrashallow junction Ge-on-Si p + n diodes have been fabricated using an epitaxial growth technique of crystalline Ge on Si substrates in a standard ASM Epsilon 2000 CVD reactor. An As-doped Ge is first depos- ited selectively at the temperature of 700 °C where most of the lattice mismatch-defects are trapped at the interface of Ge and Si and vanish within the first 300 nm of Ge growth. Under this condition, good quality single crystal Ge is grown within a layer thickness of approximately 1 lm on different window sizes up to hundreds of lm 2 . For p + n junction fabrication, the process is followed in the same reactor with a sequence of pure-Ga and then pure-B depositions, to form an ultrashallow p-doping of As-doped Ge- islands that can be metallized by Al. The term PureGaB is introduced for this technology. The I–V and C–V characterization the diodes confirms the good quality of the ultrashallow junction Ge diodes with ideality factors of less than 1.1 and reliable low saturation currents. The doping levels are shown to be such that the depletion over the diodes falls within the Ge region. Ó 2012 Elsevier Ltd. All rights reserved. 1. Introduction As a well-known material in semiconductor technology, Ge has always been interesting for its high mobility, low energy bandgap and for the match of its lattice constant with some of the III–V semiconductors such as GaAs. Nowadays, Ge is widely applied in infrared (IR) optoelectronics, as an epitaxy substrate for III–V mul- ti-junction solar cells, for SiGe alloying in state-of-the-art CMOS technology, in radiation-hard materials for the fabrication of nucle- ar-radiation detectors, and it is playing a major role in high perfor- mance fiber-optic systems [1]. All these applications of Ge together with its compatibility with Si CMOS technology and low price com- pared to III–V materials, have led to the development of numerous approaches to merging Ge and Si, most of which are based on Ge epitaxial growth on Si substrates [2–4]. However, for all these methods the 4.2% lattice mismatch between Ge and Si still presents a challenge for obtaining Ge-on-Si epitaxial growth that is not rid- den with high densities of threading dislocations and poor surface roughness. Many recent studies have aimed at overcoming the lattice-mis- match problem and some reports of good quality Ge-on-Si have ap- peared for approaches such as those using SiGe buffer layers [5,6], lateral overgrowth [7] and aspect ratio trapping (ART) by growth in high aspect ratio trenches [8,9]. However, Ge epitaxial growth on SiGe buffer layers that can be as thick as a micron or so, still results in some degree of dislocations degrading the quality of the Ge [10], and the lateral overgrowth and ART techniques developed up until now are dependent on critical nano-scale patterning and selective growth over window sizes in the 100 nm range. In contrast, the method presented in this paper, while being based on selective Ge growth in windows to a Si substrate, allows defect-free filling with c-Ge in tens-of-microns large window sizes. Moreover, the transition region from Si to Ge is kept below 300 nm in thickness. The epitaxy is performed in a standard ASM Epsilon 2000 chemical-vapor-deposition (CVD) reactor for Si/SiGe deposi- tion. For the further processing of the Ge-islands, we have made use of the fact that the available system was recently modified for merging GaAs and Si epitaxial growth in one reactor, thus allowing the integration of good-quality crystalline intrinsic/doped layers of GaAs, Ge and Si, all in one system [11]. The quality of Ge epitaxy on Si is investigated by scanning elec- tron-microscopy (SEM) and cross-section transmission electron- microscopy (TEM) analysis, not only of the Ge-islands themselves but also of GaAs deposited on the Ge, in the same growth cycle. It is shown that the inter-diffusion of Ge and Si at the interface at a deposition temperature of 700 °C leads to a sub-300 nm tran- sition with a low threading dislocation density and single crystal Ge epitaxial growth is achieved within a thickness of less than 1 lm. The doping of the Ge is studied for Ga, B and As precursors. A novel processing procedure was developed for the fabrication of p + n Ge diodes, where the p + region is created by a sequence of nm-thin pure-Ga and pure-B depositions. Unlike the Si case, where 0038-1101/$ - see front matter Ó 2012 Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.sse.2012.04.023 ⇑ Corresponding author. Tel.: +31 15 2782506; fax: +31 15 2787369. E-mail address: a.sammak@tudelft.nl (A. Sammak). Solid-State Electronics 74 (2012) 126–133 Contents lists available at SciVerse ScienceDirect Solid-State Electronics journal homepage: www.elsevier.com/locate/sse