V. V Das, R. Vijaykumar et al. (Eds.): ICT 2010, CCIS 101, pp. 274–280, 2010. © Springer-Verlag Berlin Heidelberg 2010 Graceful Degradation in Performance of WaveScalar Architecture Neha Sharma and Kumar Sambhav Pandey National Institute of Technology, Computer Science &Engineering Hamirpur (H.P.), India-177005 Neha.sm86@gmail.com, kumar@nitham.ac.in Abstract. With the advancement in technology in the field of transistors it has become easy to have millions of transistors on one dice. It is still a challenge to translate the available resources into convenient application. Many conventional processors has failed to achieve that level of performance. A new alternative to the conventional processors is the scalable WaveScalar. WaveScalar is a dataflow instruction set based execution model with low complexity and high performance features. It can run real world programs, non-real world programs without changing the language and still having the same parallelism. It is designed as a intelligent memory system where each instruction executes in its place and then communicates with its dependent. If a high-performance processor is to realize its full potential, complexity should be least. Here is this paper, we have proposed solution to reduce the complexity of the wavescalar processor without affecting its performance Keywords: Wavescalar, dataflow, ISA, parallel, performance. 1 Introduction Wavescalar is a decentralized, scalable data-flow execution based processor. This model can execute the instructions whenever the values are available locally. However, it solves many problems of dataflow model [1, 2]. One of them is providing support for conventional and imperative languages which helps in providing seamless integration between memory interfaces and multiple threads. It also helps in defining a scalable micro architecture that can execute programs that can be implemented using current process technology. Such combination of features creates a processor that can not only work as a conventional processor for programs, but which can also provide parallelism with eas ier way of designing. Wavescalar is based on intelligent cache-only computing systems. There is no central processing unit or centralized control in cache only computing environment. Instead of that, it consists of pool of processing elements that works as a central processor and cache of the processor. Wavescalar constitute of a distributed instruction cache named as WaveCache which takes the responsibility of intelligentl y executing and caching the ins tructions. In dataflow model there is no program counter to guide the flow of instructions [3, 4]. As operations on instructions are based on data driven fashion, it executes out of linear order which introduces the need