International Journal of Computer Applications (0975 – 8887) Volume 85 – No 11, January 2014 33 Verification IP for Routing Switch based on Network Layer Protocol, using SystemVerilog Dipti Girdhar School of Engineering and Technology, ITM University, Gurgaon, India Neeraj Sharma School of Engineering and Technology, ITM University, Gurgaon, India Shankar School of Engineering and Technology, ITM University, Gurgaon, India ABSTRACT Today, in the world of ASICs and system-on-chip (SoC) designs which consists of millions of transistors and gates, verification is the process which consumes most of design efforts and time [4]. One of the major stresses for the verification engineer is to verify the given design in best possible manner [5]. For this he needs to cover almost all the hidden corners cases by applying various real time test cases. This paper will assist the verification engineers to understand the flow of verification environment for packet switch IP. We will also learn about the functional coverage. The language used for verification is SystemVerilog. Keywords SystemVerilog, Verification IP, Packet switch 1. INTRODUCTION SystemVerilog is one of most preferred hardware verification language used worldwide [6]. To create any Verification IP (VIP), one need to understand various modules, which are the part of the verification environment. A design which is to be verified is commonly known as design under test (DUT). DUT is like a black box, and verification engineer is least bother about the internal schematic of the DUT. A set of specification is provided to verification engineer and he need to develop the complete VIP after reading the given specifications only. 2. COMMENCEMENT WITH DESIGN SPECIFICATION To start with, readers must recall the basic thumb rule of verification as mentioned above, that the verification engineer is provided only with the specification booklet [7]. Based on the given specifications, the verification team develops a VIP. So it is paramount to understand the given specifications. So here we will start with understanding the specifications given for DUT. We need to prepare a VIP for a simple switch which is used to drive an incoming packet to different output ports of the router. In a network, the switch acts as a router which has one input port and various output ports. In this case we have switch with one input ports and four output ports. Switch works on network layer of Open System Interconnection (OSI) model. The basic block diagram is shown in Figure 1. Figure 1: Block diagram of switch with various interfaces 2.1 Input condition for switch Input port is responsible for collecting all the incoming packets. It consists of two signals; named as data_status and data as shown in Figure 2. Both the signals are active high. Ideally, data_status signal is low, when there is no incoming packet on input port. As soon as any packet needs to enter to the switch through the input port, switch pulls up the data_status signal to high value at the rising edge of the clock. The data signal then carries the packet byte by byte. Switch releases the data_status signal to low value after receiving all the data bytes.