RESEARCH ARTICLE Copyright © 2010 American Scientific Publishers All rights reserved Printed in the United States of America Journal of Nanoscience and Nanotechnology Vol. 10, 1–5, 2010 Monte Carlo Simulation of III–V Material-Based MOSFET for High Frequency and Ultra-Low Consumption Applications Ming Shi 1 , Jérôme Saint-Martin 1 , Arnaud Bournel 1 , Hassan Maher 2 , Michel Renvoise 2 , and Philippe Dollfus 1 1 IEF, CNRS, Univ. Paris Sud, UMR 8622, Bât 220, F 91405 Orsay cedex, France 2 OMMIC/PHILIPS, F 94453 Limeil-Brévannes cedex, France High-mobility III–V heterostructures are emerging and very promising materials likely to fulfil high- speed and low-power specifications for ambient intelligent applications. The main objective of this work is to theoretically explore the potentialities of MOSFET based on III–V materials with low bandgap and high electron mobility. First, the charge control is studied in III–V MOS structures using a Schrödinger-Poisson solver. Electronic transport in III–V devices is then analyzed using a particle Monte Carlo device simulator. The external access resistances used in the calculations are carefully calibrated on experimental results. The performance of different structures of nanoscale MOS transistor based on III–V materials is evaluated and the quasi-ballistic character of electron transport is compared to that in Si transistors of same gate length. Keywords: III–V Materials, Monte Carlo Simulation, Semiconductor Device Modelling, Charge Control, Inversion Layer Capacitance. 1. INTRODUCTION Future high-speed and low power specifications for ambient intelligent functions may be not met by using the next gen- erations of Si-CMOS circuits. 12 The optimal frequency- performance/power-consumption trade-off is very difficult to achieve using this technology because of low Si carrier mobility and relatively large supply voltage required for circuit operation. Promising emerging high-mobility mate- rials, such as carbon nanotubes, semiconductor nanowires and III–V heterostructures could improve this figure of merit. The first two ones require “bottom-up” chemical syn- thesis for formation and suffer from the fundamental place- ment problem, while III–V materials are far more practical in terms of patterning. 3 Moreover, using molecular beam epitaxy (MBE) under ultra-high-vacuum (UHV) condition, amorphous mixed oxide Ga 2 O 3 (Gd 2 O 3 [GGO] 4 and single crystal Gd 2 O 3 5 may be deposited on GaAs with unpinned Fermi level at the oxide/III–V interface, interfacial den- sities of states (D it less than 10 11 cm 2 eV 1 and leak- age current as low as 10 8 A/cm 2 . Atomic layer deposited (ALD) constitutes another approach to obtaining Al 2 O 3 6 and HfO 2 7 dielectric layers on In-rich InGaAs. Excellent Author to whom correspondence should be addressed. DC device performance has been obtained with such a technique. 8 These technological developments have opened up a new era, timely for inversion-channel III–V MOS devices. The main objective of this work is to theoretically explore the potentialities of MOSFET based on III–V materials with low bandgap and high electron mobility. In Section 2, the charge control in different InGaAs- based MOS capacitors is studied using self-consistent one-dimensional (1D) Schrödinger-Poisson simulation. In Section 3, the Monte Carlo (MC) device simulator MONACO 9 is used to analyze the steady-state regime of quasi-ballistic InGaAs MOSFETs and to predict their DC intrinsic performance with a view to low power operation. Prior to this analysis the external access resistances are calibrated on I–V characteristics measured for a 70 nm- long pseudomorphic HEMT. 2. CHARGE CONTROL In this section, thanks to self-consistent Schrödinger- Poisson simulation, 10 the influence of both the inversion layer capacitance and the oxide thickness T OX on the elec- trostatic gate capacitance is studied to optimize the gate voltage swing together with avoiding intervalley transfer. J. Nanosci. Nanotechnol. 2010, Vol. 10, No. xx 1533-4880/2010/10/001/005 doi:10.1166/jnn.2010.2931 1