New oxide quality characterization for charge leakage applications using the floating-gate technique Sophie Renard a,b, * , Philippe Boivin a , Jean-Luc Autran b,1 a STMicroelectronics, ZI de Rousset, F-13106 Rousset cedex, France b L2MP, UMR CNRS 6137, Universit e Aix-Marseille 1, B^ atiment IRPHE, 49 rue Joliot-Curie, BP 146, 13384 Marseille cedex 13, France Abstract We report on the validation of a new characterization method dedicated to the tunnel oxide of electrically erasable programmable read-only memories. The present approach combines a dedicated test structure with sequential floating- gate measurements, allowing the screening of defective oxides in terms of charge leakage. We show that this floating- gate technique returns reliable information about retention capability of the thin tunnel oxide (7.5 nm) using a fast and non-destructive statistical test. Finally, quantitative information about tunnel oxide quality obtained with this new technique matches data obtained with charge-to-breakdown measurements. Ó 2003 Elsevier B.V. All rights reserved. 1. Introduction Chargeleakagethroughatunneloxideisoneof the main issues for non-volatile memories (NVM) technologies [1]. Since this oxide potentially represents the most likely leakage path from the floating gate, from the manufacturing point- of-view, it is thus of prime importance to monitor oxide quality in terms of charge retention. Recently, we developed a new wafer-level characterization procedure [2] to detect defective tunnel oxides using the floating-gate (FG) tech- nique. This technique has been used in the last few years for various applications such as character- ization of hot carrier effects [3], measurement of capacitor matching [4], and metrology of ex- tremely low gate currents (typically below 10 15 A) [5,6]. In this study, we report a detailed comparison between reliability data obtained by this improved FG technique and classical charge-to-breakdown (Q BD ) measurements. In order to perform this comparison on a large number of devices, we de- signed a realistic memory cell-based test structure allowing automatic wafer-level test measurements. In the following, we describe the measurement technique, the dedicated test structure, and we present statistical results obtained on a population of 20 devices. Consequences on tunnel oxide reli- ability and characterization are also discussed. * Corresponding author. Tel.: +33-4 42 68 84 66; fax: +33-4 42 68 88 99. E-mail addresses: sophie.renard@st.com (S. Renard), au- tran@up.univ-mrs.fr (J.-L. Autran). 1 Tel.: +33-4 96 13 97 17; fax: +33-4 96 13 97 09. 0022-3093/03/$ - see front matter Ó 2003 Elsevier B.V. All rights reserved. doi:10.1016/S0022-3093(03)00199-6 Journal of Non-Crystalline Solids 322 (2003) 179–182 www.elsevier.com/locate/jnoncrysol