Applied Physics Research; Vol. 4, No. 4; 2012 ISSN 1916-9639 E-ISSN 1916-9647 Published by Canadian Center of Science and Education 18 Impact of Injected Charges, Clock Noise and Operational Amplifier Imperfections on the Sample and Hold (SH) Overall Performance Ababacar Ndiaye 1 , Daniel Dzahini 2 , Pape A. Ndiaye 1 , Cheikh M. F. Kébé 1 & Vincent Sambou 1 1 Centre International de Formation et de Recherche en Energie Solaire (CIFRES), Ecole Supérieure Polytechnique-UCAD, Dakar-Fann, Sénégal 2 Laboratoire de Physique Subatomique et de Cosmologie, 53 avenue des Martyrs, Grenoble Cedex, France Correspondence: Ababacar Ndiaye, CIFRES - Ecole Supérieure Polytechnique, Université Cheikh AntaDiop de Dakar, BP: 5085 Dakar-Fann, Sénégal. Tel: 221-77-654-6393. E-mail: ababacar.ndiay@gmail.com Received: September 10, 2012 Accepted: September 24, 2012 Online Published: October 10, 2012 doi:10.5539/apr.v4n4p18 URL: http://dx.doi.org/10.5539/apr.v4n4p18 Abstract The growing use of digital processing in analog environments underlines the importance of Analog Digital Converter (ADC) occurrence in circuitry. The quality and reliability of the conversion are closely linked to the Sample and Hold (SH) performance. Actually SH is a key component in the Analog/Digital chain. The Operational Amplifier being at the heart of the SH influences its output and subsequently impacts the reliability and quality of the conversion. In this paper we present the impact of both Operational Amplifier intrinsic characteristics and external factors such as injected charges, and clock noise on the SH overall performance. We limit our consideration to the offset and parasite capacities as the only relevant Operational Amplifier intrinsic characteristics. We’ll introduce the Operational Amplifier and SH functional characteristics then address the impact of each of these parameters on the SH output which the ADC works on. A behavioral description of the Operational Amplifier based on the Verilog-A language under Cadence approach is used. Furthermore a behavioral/analog mixed description is considered for the SH: the Operational Amplifier described behaviorally in Verilog-A is associated to analog components in Cadence libraries and CMOS switches act as SH. However this simplistic approach doesn’t reflect all the challenges involved, because it is not enough to connect a SH to ADC to flawlessly digitalize an analog signal. The SH architecture and the Operational Amplifier characteristics play also a role for a reliable sampling and therefore a good quality conversion prospect.In this study the SH performance is evaluated through its non-linearity which in turn determines the sampling accuracy a key factor for a conversion. This study is as shown that small amplitude signals are more sensible to sampling errors related to Operational Amplifier offset. Furthermore the stray capacities attenuate the SH signal output. The injected charges and the clocknoise as strongly interrelated contribute to the non-linearity of the conversion chain. Keywords: ADC, SH, operational amplifier, injected charges, offset, clock noise, stray capacities 1. Introduction Today the majority of the circuits and electronic systems use the digital processing of the acquired data.However in Nature phenomena are analogic in essence; therefore the need for converting those analogical signals numerically arises. This conversion is made through an ADC (Analog Digital Converter), in which the Sample and Hold (SH) circuit placed upstream is a key component. As depicted in Figure 1, the SH handles the signal both at the entry and at any further stage in the ADC pipeline. The operational amplifier as fundamental component is shown in Figure 2, representing an elementary SH. This way of presenting analogical to digital conversion is not however free from imperfections: it is not enough to simply connect an SH to an ADC to flawlessly digitize an analogical signal. Structures of the SH and the Operational Amplifier are determining as shown in the subsequent sections for a good sampling and thus a reliable conversion. The work presented in this paper consists the one hand developing and to validate a behavioral model of Operational Amplifier under the Cadence environment. Then, a study of impact on the SH of Operational Amplifier offset, the injected charges, the stray capacities and the clock noise will be presented.