Evaluating Alpha-induced Soft Errors in Embedded Microprocessors P. Rech 1 , S. Gerardin 1 , A. Paccagnella 1 , P. Bernardi 2 , M. Grosso 2 , M. Sonza Reorda 2 , D. Appello 3 1 Università di Padova, Dipartimento di Ingegneria dell’Informazione, Padova, Italy {paolo.rech, simone.gerardin, alessandro.paccagnella}@dei.unipd.it 2 Politecnico di Torino, Dipartimento di Automatica e Informatica, Torino, Italy {paolo.bernardi, michelangelo.grosso, matteo.sonzareorda}@polito.it 3 STMicroelectronics, Agrate Brianza (MI), Italy {davide.appello@st.com} Abstract - This paper presents the results of Alpha Single Event Upsets tests of an embedded 8051 microprocessor. Cross sections for the different memory resources (i.e., internal registers, code RAM, and user memory) are reported as well as the error rate for different codes implemented as test benchmarks. Test results are then discussed to find the contribution of each available resource to the overall device error rate. I. INTRODUCTION Electronic devices are constantly affected by radiation effects even at sea-level. High-energy and thermal neutrons generated by the interaction of cosmic rays with terrestrial atmosphere and alpha particles emitted by chip package materials may generate different kinds of errors in electronic devices [1-4]. Errors induced by alphas can be reduced using Low Alpha and and Ultra Low Alpha molding compounds which, however, are more expensive than standard materials. Experimentally determining the device sensitivities to the different impinging particles allows designers to evaluate if the device is employable in those fields where high product reliability is a major concern, such as the automotive and the biomedical. Today’s electronic devices often correspond to Systems on Chip (SoCs), which include several cores, each possibly requiring different specific implementation techniques: therefore, the susceptibility to radiation is not the same for all parts of the system. Efficient strategies are required to collect data from each resource in the embedded cores to gain information about radiation- induced effects. Experimentally determining the error rate of each resource is not trivial, and may be achieved reusing some of the Design for Testability/Diagnosability (DfT/D) circuitry added to chips for manufacturing tests. In the case of embedded microprocessors, different resources (e.g. registers, memory modules, peripheral cores) may be affected by radiation, and each resource may have different sensitivity. This paper describes in detail the setup adopted during radiation tests, including the employed on-chip DfT/D structures, a suitable test board and ad-hoc software procedures for determining the sensitivity of different devices in a microprocessor-based system. To understand the overall chip radiation sensitivity it is not sufficient to calculate the induced error rate of each resource. The corruption of one resource, in fact, not necessarily leads to a functional error, as, for instance, it may not be used in the running application, or the data it stores may be obsolete. Therefore, the cross-section measure for different resources gives an upper bound to the sensitivity of a chip running user applications. Radiation tests results permit to measure the device sensitivity as well as the failure rate of a specific application. On the other hand, knowing which resources are more likely to fail and how errors propagate gives indication on hardware/software design rules for lowering device and running program sensitivity. Fault-injection techniques are traditionally applied to estimate errors criticalities and propagations, as one resource is artificially corrupted at a time and the overall system functionality is checked. The probability of error to occur must be appropriate and adapted to the experimentally measured sensitivity. For instance, if registers bits have a higher sensitivity than Code SRAM ones, the fault-injection system should keep this into account to give realistic results. As a case study, we describe the test structures and techniques implemented on a chip manufactured by STMicroelectronics in a 90 nm technology including an 8051 microprocessor. Radiation test results are provided for the device memory resources and for ad-hoc implemented codes. The rest of the paper is organized as follows: section 2 reviews the basic concepts about radiation testing and provides a quick overview on the used DfT structures; section 3 summarizes our idea and intent for this work; 69 978-1-4244-4595-0/09/$25.00 c  2009 IEEE