Sampling Jitter Estimation and Mitigation in Direct RF Sub-Sampling Receiver Architecture Ville Syrjälä and Mikko Valkama Tampere University of Technology Department of Communications Engineering P.O. Box 553, FI-33101, Tampere, Finland ville.syrjala@tut.fi, mikko.e.valkama@tut.fi Abstract—The sampling jitter is particularly problematic in systems where high-frequency signals are sampled. This paper addresses the sampling jitter estimation and cancellation task in the direct RF sub-sampling type radio receivers. The proposed jitter estimation method is based on carefully injecting or super- imposing an additional reference signal to the received signal at sampler input. Proper digital signal processing methods are then devised and applied to estimate the sampling jitter realizations from the obtained jittered samples. Using these jitter estimates, combined with proper jitter modelling, the jitter effects can then be efficiently removed from the actual received signal. Careful performance analysis of the overall estimation-cancellation scheme is also carried out using computer simulations with 3GPP LTE type multicarrier signals, assuming also different amounts of RF filtering prior to RF sub-sampling stage. Keywords—Sampling jitter; phase noise; mitigation; direct RF sampling; bandpass sampling; sub-sampling I. INTRODUCTION Sampling of high-frequency signals, or signals with power- ful interference at nearby frequencies, poses relatively high requirements for the timing accuracy of the sampling process [7]. In traditional communications receivers, down-conversion and analogue filtering are used to bring the signal down to lower frequencies and attenuate most of the interference near the interesting frequencies [5]. This results into relatively relaxed requirements for the dynamics and timing accuracy of the sampling circuitry. However, when emphasizing radio flexibility and re-configurability, more and more of the selec- tivity filtering is moved to digital domain. Similarly from the frequency-translations point of view, applying sampling al- ready to higher-frequency signals is one of the main trends currently. Under these working assumptions, timing inaccura- cies in the sampling process, called sampling jitter, become a severe problem. From the future wireless communications point of view, understanding, modelling and mitigation of the sampling jitter is thus a very interesting and important topic. Sampling of very high-frequency signals with possibly powerful interferers at neighbouring frequencies is culminated in the so-called direct RF sampling (DRFS) receiver architec- ture. DRFS itself is, as the name implies, a receiver architec- ture in which the sampling of the incoming signal is done already at the radio frequencies (RF). DRFS minimizes the amount of analogue components in the receiver, thus empha- sizing re-configurability and also potentially minimizing size, power consumption and costs of the receiver compared to more traditional radios. However, the DRFS concept still has many practical implementation issues to be solved [5], [11], and it is thus not commonly considered feasible especially for mobile terminal receivers with today’s implementation tech- nologies. The most notable problem with the DRFS approach is that it indeed poses very high demands for the quality of the sampling process. With current technologies, the combined requirements of relatively high sampling frequency and high resolution and timing accuracy for the used sampling circuitry result into relatively high power consumption, which in turn is one of the main concerns in mobile terminals. To circumvent this, digital signal processing (DSP) methods can be developed to lower the quality requirements for the sampling process. In the literature, DSP-based estimation and mitigation of sampling jitter is not too widely researched because in most of today’s receiver architectures, sampling takes place at fairly low frequencies. However, as indicated earlier, this might not be the case in near future, since minimizing the amount of analogue parts in receivers becomes more and more interest- ing. Furthermore, DSP capabilities of the mobile devices are continuously increasing. Recently, in [9], use of phase noise mitigation techniques [12] in mitigation of sampling jitter in bandpass sampling receivers was proposed for orthogonal frequency division multiplexing (OFDM) systems. In addi- tion, the authors of [6] have proposed a technique to remove sampling jitter effects from general narrowband signals with help of a reference tone. In this paper, the idea of carefully designing and injecting a reference tone on top of the received signal at the sampler input signal is further developed. This paper first proposes an efficient technique to estimate the sampling jitter realizations with the help of such reference tone. The estimates of the jitter realizations are then used to mitigate the effects of the sampling jitter from the actual received waveform, without the limitations of narrowband signals and small jitter values as was assumed in [6]. Special emphasis in modelling and algorithm development is put to the DRFS receiver case where only partial selectivity is im- plemented at RF prior to sampling. This work was supported by the Finnish Funding Agency for Technology and Innovation (Tekes, under the project “Advanced Techniques for RF Impairment Mitigation in Future Wireless Radio Systems”), the Academy of Finland, the Technology Industries of Finland Centennial Foundation, Finnish Foundation for Technology Promotion, and TUT Graduate School.