1970 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 9, SEPTEMBER 2003 New Method to Measure Emitter Resistance of Heterojunction Bipolar Transistors Jonathan Brereton Scott, Senior Member, IEEE Abstract—The null in third-order intermodulation as a func- tion of emitter current in a bipolar transistor is exploited to find emitter Ohmic resistance. The measurement can be carried out using only low-cost equipment and a scalar receiver. Results for an heterojunction bipolar transistor (HBT) are compared with those found using a vector network analyzer and a sophisticated extrac- tion algorithm. The method is extended to simultaneously deter- mine thermal resistance, , and to obtain a most precise esti- mate of emitter resistance. Index Terms—Bipolar transistor, distortion, emitter resistance, heterojunction bipolar transistor, modeling, parameter extraction, thermal resistance. I. INTRODUCTION T HE intrinsic emitter resistance of any bipolar transistor, , is typically one of the first model parameters ex- tracted. It has significant impact on device performance and many of the parameters extracted subsequently depend upon knowing within a few percent, and allowing for its effects upon measured data. For this reason it is a subject that has re- ceived a lot of attention. DC techniques do not generally give sufficiently accurate re- sults for modeling purposes [1]–[3]. One of the most popular techniques published to date is that of Maas and Tait [3], which appears in modified form in more comprehensive reports such as [4]. The method consists of noting that for a bipolar transistor in common-emitter (CE) configuration (1) while the dynamic resistance part (2) where is the dc emitter bias current. The value of as a function of is found from S-parameters and plotted against . Thence is found by extrapolating back to the point. is typically nearly real up to relatively high fre- quencies, and the phase angle provides a built-in check as to the correct operation of the measurement. The author’s laboratory employs refinements to this technique, but the process is sub- stantially as described. Manuscript received March 31, 2003; revised June 11, 2003. The review of this paper was arranged by Editor J. Burghartz. The author is with the Microwave Technology Center, Agilent Technologies, Santa Rosa, CA 95403 USA (e-mail: jonathanscott@ieee.org). Digital Object Identifier 10.1109/TED.2003.815600 This “ ” method has drawbacks. It depends upon the mea- surement of small-signal, 2-port impedance (usually in the form of S-parameters), in turn requiring a Vector Network Analyzer (VNA). The VNA must be calibrated and the device measure- ments may also need to be de-embedded. This entails a signifi- cant overhead if one seeks to check only the value of rather than carry out a complete extraction procedure. The impedance must be measured as a function of bias, meaning a lengthy mea- surement procedure that can be intolerable in a production en- vironment. The post-processing of the data can be involved so it is not suited to hand calculation or to production test execu- tive programs that do not support complicated programming. Finally, VNAs are expensive and may not be available to all laboratories. The following section describes the theory of an alternative technique that is much faster, requires less data, and only low-cost equipment. Section III compares measured results for the new technique with the technique from [3]. Section IV considers the impact of device heating. II. TRANSISTOR LINEARITY It has been known for many years that the exponential char- acteristic of a bipolar transistor in common-emitter (CE) con- figuration gives rise to a null in the third-order intermodulation (IM3) product appearing in the collector current. This is suc- cinctly described in an excellent, recent tutorial paper on device distortion [5]. In [5], it is pointed out that the null occurs when there exists an emitter degeneration resistance such that the emitter current drops a dc voltage exactly equal to half the thermal voltage, . Mathematically, (3) where (4) The emitter degeneration resistance in this formula includes all resistance contributed externally to the dynamic, junction- related resistance. When no resistance is intentionally added, it equals the intrinsic parasitic resistance of the device (plus of course any uncalibrated contribution from the measurement system). The null in IM3 occurs when (5) 0018-9383/03$17.00 © 2003 IEEE