1474 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 53, NO. 6, JUNE 2006 Briefs Enhancement-Mode AlGaN/GaN HEMTs on Silicon Substrate Shuo Jia, Yong Cai, Deliang Wang, Baoshun Zhang, Kei May Lau, and Kevin J. Chen Abstract—High-performance enhancement-mode AlGaN/GaN HEMTs (E-HEMTs) were demonstrated with samples grown on a low-cost silicon substrate for the first time. The fabrication process is based on a fluo- ride-based plasma treatment of the gate region and postgate annealing at 450 ◦ C. The fabricated E-HEMTs have nearly the same peak transconduc- tance (G m ) and cutoff frequencies as the conventional depletion-mode HEMTs fabricated on the same wafer, suggesting little mobility degrada- tion caused by the plasma treatment. Index Terms—AlGaN/GaN, enhancement mode, fluoride, HEMT, plasma treatment, silicon substrate, threshold voltage. I. INTRODUCTION Most of the development in GaN-based HEMT technology has been focused on depletion-mode AlGaN/GaN devices [1]–[4] that feature negative gate threshold voltage. Enhancement-mode (E-mode) HEMT (E-HEMT) devices, which exhibit a positive threshold voltage, provide extra benefits in many applications. For RF/microwave applications, the E-HEMTs enable the elimination of the negative polarity supply voltage, leading to a reduced circuit size and cost. For digital appli- cations, E-HEMTs integrated with depletion-mode (D-mode) HEMTs (D-HEMTs) can be used in direct-coupled FET logic (DCFL) circuits that have much simpler circuit configurations compared to those im- plemented by D-HEMTs-based technologies. However, the fabrication of E-HEMTs in III-nitride materials is difficult due to the large amount of polarization charges in AlGaN/GaN heterostructures. To date, most E-HEMTs have been fabricated by reducing the gate-to-channel distance via thinner barrier layer growth [5] or recess etch [6]–[8]. In conventional AlGaN/GaN HEMT structures, where Al composition is in the range of 15%–35% and the AlGaN-barrier thickness is around 20 nm, the decrease in AlGaN thickness may result in a reduced polarization-induced two-dimensional electron gas (2DEG) density. Consequently, the access resistance could be raised, degrading the extrinsic transconductance. The recessed-gate approach requires additional pregate annealing and additional gate-level photolithog- raphy, which implies that the gate recess and gate metallization are not self aligned. A novel approach is proposed by our group recently on samples grown on a sapphire substrate. The technique employs a self-aligned fluoride-based plasma treatment of the gate region and postgate annealing [9], maintaining a low-access resistance. Confirmed by a second ion mass spectroscopy (SIMS) measurement, the plasma treatment can effectively incorporate immobile negatively charged fluorine ions into an AlGaN barrier, raise the conduction band, Manuscript received November 10, 2005; revised February 28, 2006. This work was supported in part by the Research Grant Council of Hong Kong Government under Competitive Earmarked Research Grants (CERG) HKUST6317/04E and HKUST6215/03E. The review of this brief was arranged by Editor M. Anwar. The authors are with the Department of Electrical and Electronic Engineer- ing, Hong Kong University of Science and Technology, Kowloon, Hong Kong (e-mail: eekjchen@ust.hk). Digital Object Identifier 10.1109/TED.2006.873881 and shift the threshold voltage to a positive value. For high-volume applications, such as digital integrated circuits, the commonly used high-performance SiC substrates have severe cost disadvantages. The sapphire substrates are low cost, but feature inefficient heat dissipation due to their poor thermal conductivity. Recently, there have been increasing activities in growing AlGaN/GaN HEMT structures on silicon substrates [10]–[15], which offer advantages including large- size substrate, low-cost and good thermal conductivity. The greatest challenge concerning GaN growth on an Si substrate is to manage the mismatch in the thermal expansion coefficients between GaN and Si so that cracks will not occur on the epitaxial grown films. In this brief, AlGaN/GaN E-HEMTs are demonstrated on silicon substrates for the first time. Crack-free AlGaN/GaN HEMT structures were grown on silicon substrates. Using fluoride-based plasma treat- ment, D-HEMTs with a threshold voltage of −3.3 V are converted to E-HEMTs with a 0.5-V threshold voltage, allowing a monolithic integration of E-HEMT and D-HEMT for digital applications. II. MATERIAL GROWTH AND DEVICE FABRICATION The heterostructure layers employed in this brief were epitaxially grown by metal–organic chemical vapor deposition (MOCVD) on a 2-in (111) silicon substrate. It consists of a 30-nm high-temperature AlN nucleation layer grown at 1150 ◦ C, followed by a 1-μm-thick GaN buffer that has a 10-nm-thick low-temperature AlN interlayer grown at 760 ◦ C inserted in the middle. Then, the Al 0.3 Ga 0.7 N barrier is grown, which consists of a 3-nm undoped spacer, a 15-nm doped (Si doped, 5 × 10 18 cm −3 ) carrier supply layer, and a 2-nm undoped cap layer. Owing to the optimized interlayer, the grown sample is crack free. The 2DEG sheet electron density is around 1.0 × 10 13 cm −3 in the as-grown sample and the 2DEG mobility is around 800 cm 2 /V · s. For device processing, both D-HEMT and E-HEMT are imple- mented on the same wafer. Device mesa was formed using Cl 2 /He plasma dry etching in an Surface Technology Systems plc (STSs) inductively coupled plasma reactive ion etching (ICP-RIE) system fol- lowed by the source/drain ohmic contact formation with Ti/Al/Ni/Au annealed at 850 ◦ C for 30 s. The ohmic contact resistance was typically measured to be 0.7 Ω · mm by TLM method. Ni/Au e- beam evaporation and liftoff were carried out subsequently to form the gate electrodes. E-HEMTs underwent identical processing as D- HEMTs, except for an additional fluoride-based treatment before the gate metal deposition. This treatment employs CF 4 plasma in an STS RIE system at a power 170 W for 120 s after gate regions were open by photolithography. The gas flow was controlled to be 150 sccm during the plasma treatment. D-HEMTs are protected by photoresist during treatment and not affected. After the gate metal deposition, the sample was annealed at 450 ◦ C in N 2 ambient for 10 min to recover the plasma induced damage. In the plasma treated devices, experiment results show that the pinchoff voltage shift will increase with both the plasma power and treatment time. However, higher energy treatment will cause unrecoverable damages and degradation of electron mobility. The temperature of the postgate annealing was chosen to be 450 ◦ C out of consideration of avoiding degradation of the gate Schottky contacts [16]. All the D/E-mode devices stated in this article have 1-μm gate length and 100-μm gate width with a source–gate spacing of L SG =1 μm and a gate-drain spacing of L GD =2 μm. 0018-9383/$20.00 © 2006 IEEE