Published in IET Circuits, Devices & Systems Received on 1st November 2007 Revised on 8th September 2008 doi: 10.1049/iet-cds:20080070 ISSN 1751-858X High-performance noise-tolerant circuit techniques for CMOS dynamic logic F. Frustaci P. Corsonello S. Perri G. Cocorullo Department of Electronics, Computer Science and Systems, University of Calabria, Arcavacata di Rende, 87036 Rende (CS), Italy E-mail: p.corsonello@unical.it Abstract: Dynamic CMOS gates are widely exploited in high-performance designs because of their speed. However, they suffer from high noise sensitivity. The main reason for this is the sub-threshold leakage current flowing through the evaluation network. This problem becomes more and more severe with continuous scaling of the technology. A new circuit technique for increasing the noise tolerance of dynamic CMOS gates is studied. A comparison with previously reported schemes is presented. Simulations proved that, when 90 nm CMOS technology is used to realise wide fan-in gates, the proposed design technique can achieve the highest level of noise robustness. A 16 bits OR gate designed as proposed here shows a maximum unity noise gain of 675 mV, a computational delay of 115 ps and an energy dissipation of 33 fJ. Moreover, at the parity of energy-delay product (EDP), the novel approach achieves a noise robustness 10% higher than the most efficient technique existing in the literature, whereas, at the parity of noise robustness, it exhibits an EDP 33% lower. 1 Introduction Owing to the aggressive scaling down of the technology to the deep sub-micrometer regime, noise immunity is becoming a very important issue in the design of VLSI chips. The term ‘noise’ in digital integrated circuits generally refers to any possible event that may cause the voltage at a node to vary from its nominal value. There are different sources of noise in deep-submicron circuits. They are mostly related to crosstalk, small variations of the nominal supply voltage value, charge sharing and leakage current. The leakage current is the most critical, since in digital circuits it exponentially increases with the continuous shrinking of the MOS transistor dimensions [1, 2]. In fact, in order to limit dynamic energy consumption, the supply voltage is reduced in each new technology node. At the same time, the threshold voltage (V TH ) of the MOS transistor is scaled down to assure high performance. As a consequence, the sub-threshold leakage current continually increases, since it is exponentially dependent on 2V TH . Furthermore, the continuous reduction of the gate oxide thickness causes an exponential increase of the gate leakage current because of the enhanced tunnelling of the carriers through the oxide itself. Together with the increase of transistor density, specific design styles have also been aggressively exploited in order to achieve high performance. Here, it is the case of the domino logic design style, which is faster than the static CMOS. Moreover, domino gates are more compact, especially when they have a wide fan-in. Wide fan-in domino gates are often employed in the critical path of high- performance chips, such as in general purpose microprocessors or digital signal processors. As an example, wide fan-in OR gates and MUXs are used in the design of high-performance register files [3]. Domino gates suffer from higher noise sensitivity than their static CMOS counterparts. This is because of their low switching threshold voltage, which is equal to the V TH of the pull-down NMOS devices. Noise immunity has become a great concern, especially in the design of high fan-in gates. This is because of the high number of transistors and circuit branches, which cause more possible paths for gate and sub-threshold leakage currents. Recently, several techniques have been proposed to reduce the leakage noise sensitivity of high fan-in footless domino gates [4–13]. All the existing techniques improve the noise IET Circuits Devices Syst., 2008, Vol. 2, No. 6, pp. 537–548 537 doi: 10.1049/iet-cds:20080070 & The Institution of Engineering and Technology 2008 www.ietdl.org