https://iaeme.com/Home/journal/IJARET 111 editor@iaeme.com International Journal of Advanced Research in Engineering and Technology (IJARET) Volume 12, Issue 5, May 2021, pp. 111-125, Article ID: IJARET_12_05_011 Available online at https://iaeme.com/Home/issue/IJARET?Volume=12&Issue=5 ISSN Print: 0976-6480 and ISSN Online: 0976-6499 DOI: 10.34218/IJARET.12.5.2021.011 © IAEME Publication Scopus Indexed COMPLEX BINARY SUBTRACTOR DESIGNS AND THEIR HARDWARE IMPLEMENTATIONS Tariq Jamil, Medhat Awadalla, and Iftaquaruddin Mohammed Department of Electrical and Computer Engineering, Sultan Qaboos University, AlKhod, Oman ABSTRACT Complex Binary Number System (CBNS) is (-1+j)-based binary number system which facilitates both real and imaginary components of a complex number to be represented as single binary number. In this paper, we have presented two designs of nibble-size complex binary subtractors (decoder-based, minimum-delay) and implemented them on various Xilinx FPGAs. Key words: complex binary, complex number, decoder, subtractor, minimum delay. Cite this Article: Tariq Jamil, Medhat Awadalla, and Iftaquaruddin Mohammed, Complex Binary Subtractor Designs and their Hardware Implementations, International Journal of Advanced Research in Engineering and Technology, 12(5), 2021, pp. 111-125. https://iaeme.com/Home/issue/IJARET?Volume=12&Issue=5 1. INTRODUCTION Complex numbers play important roles in various areas of electrical and computer engineering but their representation and treatment in the realm of computing are based on a divide-and- conquer technique wherein real part of the complex number is dealt with separately and imaginary part of the complex number is handled separately. Thus, subtraction of two complex numbers (a + jb) and (c + jd) involves two separate subtractions: (a − c) for the real parts and (b − d) for the imaginary parts. To facilitate single-unit representation of a complex number which will ultimately result in the reduction of arithmetic operations for the real and imaginary components of complex numbers, Complex Binary Number System (CBNS) with (-1+j)-base has been proposed in the scientific literature [1-3]. In an earlier paper [4], we have presented designs of CBNS adder circuits. In continuation with our efforts to establish CBNS within the realm of computer arithmetic, in this paper, we are going to present designs of nibble-size complex binary subtractor circuits and their implementations on various Xilinx FPGAs.