Analog Integrated Circuits and Signal Processing 5, 219-234 (1994) © 1994 Kluwer Academic Publishers, Boston. Manufactured in The Netherlands. Configurable CMOS Multiplier/Divider Circuits for Analog VLSI MOHAMMED ISMAIL,1 ROBERT BRANNEN, 1 SHIGETAKA TAKAGI2 NOBUO FUJII,2 NABIL I. KHACHAB, a RONNY KHAN,4 AND ODDVAR AASERUD 4 1The Ohio State University, Department of Electrical Engineering, Columbus, OH 43210 2Tokyo Institute of Technology, Department of Physical Electronics 2-12-10okayama, Meruro-Ku, Tokyo 152, Japan 3Electrical Engineering, Kuwait University, Safat 13060, Kuwait 4Norwegian Institute of Technology (NTH), University of Trondheim, Department of Physical Electronics, iV-7034 Trondheim, Norway Received June 15, 1993. Abstract. The design of five simple CMOS opamp based multipleffdivider circuits is presented. Each two opamp and ~fixMOSFET transistor circuit simultaneously achieves four-quadrant multiplication and division. Applica- tions of the new circuits in analog signal processing and neural networks are discussed. The multiplier/divider circuits are all insensitive to MOS intrinsic parasitic capacitances. They do, however, exhibit different sensitivities to opamp finite unity-gain bandwidth. These sensitivities may be mitigated using the configurability property of the circuits. Finally experimental results are provided to support some of the theoretical claims. 1. Iv~troduction Analog multipliers and dividers have their wide range of applications in traditional analog signal processing, telecommunication, and electronic systems [1, 2], as well as in analog computational systems based on bio- logical "neural" paradigms [3, 4]. So far, multiplier designs have received much of the attention. These design procedures vary from the continuous-time tran- sistor level approach to the switched-capacitor tech- nique. Multipliers designed at the transistor level suffer from lengthy and complicated design procedures. The switched-capacitor techniques require many clock schemes, more chip area, and z-domain designs. Moreover, these circuits suffer from many problems, such as clock feedthrough, band-limited signals, and aliasing. In addition, continuous-time anfialiasing and smoo~ing filters are needed at the input and the out- put, respectively. Dividers, on the other hand, require more complex circuitry, and in their simplest form they employ a multiplier in the feedback path of an invert- ing amplifier. This article presents five simple continuous-time multiplier/divider circuits that are based on MOS tran- sistors operating in the linear (triode) region [5-7] and discusses their application in analog VLSI signal and information processing. Section 2 presents the design and operating principles for all five circuits. Many applications of the new cell in analog signal process- ing are discussed in Section 3. AMOS implementation of the synaptic weights of the Hopfield feedback neural network is introduced in Section 4. Design considera- tions and nonideal effects are discussed in Section 5. Experimental results based on a discrete implementa- tion using CD4007 PMOS transistors and CA3060 CMOS opamps are presented in Section 6. 2. Design and Operating Principles Consider the multiplier/divider cell of figure 1. All MOSFETs are biased in the triode region. The positive and negative inputs of both opamps are always tied directly to ground or are at virtual ground. Transistors