Towards a FPGA-based Universal Link for LVDS Communications: A First Approach Giancarlo Patiño * , Luis Sánchez * , James Lyke # and Víctor Murray *,^ * Department of Electrical Engineering, Universidad de Ingeniería y Tecnología – UTEC, Lima, Peru # U.S. Air Force Research Laboratory, Albuquerque, New Mexico, USA ^ Department of Electrical and Computer Engineering, University of New Mexico, Albuquerque, New Mexico, USA Abstract—We present a first approach to a FPGA-based universal link to handle different low-voltage differential signaling (LVDS) connections without changing the configuration of the transmitters or components. LVDS is one of the fastest and cheapest electrical digital signaling standards and, because of many electrical advantages compared to other standards, LVDS is used now by different applications from TV or LCD communications to spacecraft network communications like SpaceWire. However, the number of physical wires to have a full- duplex communication using LVDS is four and, in a network communication system, the total number of wires will be four multiplied by the number of individual connections. We present a first approach to a scalable hardware implementation to handle different LVDS connections using only one LVDS connection for a simplex system. The hardware presented here has been tested up to four input signals and up to 8 bits per package to transmit with promising results. In this first approach, we show the simulated results based on an Atlys board with a Spartan 6 FPGA. Keywords—LVDS, FPGA, multiplexing, universal link I. INTRODUCTION Low-voltage differential signaling (LVDS) is an electrical digital signaling standard commonly used in consumer (TV, DVD, and LCD panels, for example), industrial, and aerospace (for example, SpaceWire, developed by the European space agency) applications [1, 2]. LVDS is a popular choice for physical layer transport of digital information due to its speed, low power consumption, and inherent simplicity [3]. The basic implementation of LVDS requires only two wires, upon which logical zero (‘0’) and one (‘1’) states are defined by small changes in voltage and current (e.g., 3.5mA and less than 2.5V) [4, 5] at a data transfer rate limited only ultimately by the performance of driver and receiver, and signal integrity of the transmission wiring. Owing to the speed and simplicity of the LVDS, it is possible in principle to use it as a transport medium for rendering other link technologies, such as the inter-integrated circuit (I2C) or serial peripheral interface (SPI). In this case, each link technology is converted with an adapter to LVDS, where the data in the original link is encoded on LVDS where it is transported to a reciprocal adapter that recovers the original data in the format of the original link. The information impressed on the LVDS link includes not only the original data, but also other auxiliary data associated with control and recovery. In principle, this concept could be extended to encode multiple copies of links on both sides of an adapter to include multiple copies of LVDS signals. Also, it might be possible to mix different types of links, so that this transport could render a mixture of I2C, SPI, LVDS (and other) interfaces from one point in a system and transparently transport these interfaces to another location on a “universal link,” where with the right adapter, these mixed interfaces are recovered in a way that is transparent to the application. We would ideally be able to perform this for duplex, multi-drop, and other connection schemes, with the appropriate protocols and adapter design. As a step towards this “universal link,” we explore first the case of transporting several LVDS links in a multiplexed for onto a single LVDS transport link. We consider in this case a simplex system (i.e., LVDS links all sending information in the same, single direction). The adapter hardware should be able to multiplex and demultiplex the signals such that any information in each individual connection does not experience any changes (subject to specified link performance constraints), with any reconfiguration of the transmitters or individual components. The primary motivation even for this limited case is wiring reduction, albeit at the expense of performance. In other words, we can route N signals over a single LVDS pair at the cost of reducing performance by a least 1/N of the maximum data rates. We are of course focusing on those cases where the reduction in performance is acceptable. The work described in this paper focuses on developing a FPGA-based universal link that can transmit multiple LVDS communications using a single LVDS communication link. Fig. 1a depicts a system with N communication pairs working individually. With a FPGA-based adapter design, we aggregate those connections and transmit them in a groomed form using a single LVDS connection forming a multiplexer-link- demultiplexer circuit, as shown in Fig. 1b. Note that in this case definition, the N individual links (c 0 , c 1 , …, c N-1 in Fig. 1) do not experience any apparent change in normal operation, since the universal link by design can handle the bandwidth (i.e., can sample the and regenerate the N channels of information fast enough and in a way that is transparent). A small time delay (which does not affect data integrity) will result in this scheme owing to the propagation and gate-to-gate timing delays associated with the conversion process. A variety of protocol concepts can be devised to represent how a sequence of data from several parallel links could be serialized onto a single link. We employed a round-robin