“Bottom-up” Approaches for Nanoelectronics 137 X “Bottom-up” Approaches for Nanoelectronics Mrunal A. Khaderbad 1 , Arindam Kushagra 1 , M. Ravikanth 2 and V. Ramgopal Rao 1 1 Centre for Excellence in Nanoelectronics, EE Department, IIT Bombay, 2 Department of Chemistry, IIT Bombay, Powai, Mumbai-400076 India 1. Introduction Over the last 40 years, feature sizes in complementary metal oxide semiconductor (CMOS) technologies have been scaled from 3 μm to the current sub-50 nm using the “top-down” scaling techniques (Nowak, 2002). This “scaling” has resulted in an increased processing power and transistor density while reducing the cost per transistor (Chao Li et al., 2007). These classical methods employ a sequence of deposition, pattern definition, doping, lithographic and etching steps to build solid-state semiconductor devices and integrated circuits. As the process technologies scale beyond the sub-10nm feature sizes, above fabrication methods result in increased process costs, variability and longer fabrication turnaround times. To push the CMOS technology to its limits and to reap the benefits of scaling, non-traditional alternatives are needed while fabricating devices. One such approach is the use of “bottom-up” nanotechnologies or even a combination of the bottom- up and the “top-down” fabrication methodologies (Wei et al., 2007). In the bottom-up approach, analogous to the biological systems, atoms or organic molecules are self- assembled to build electronic structures with novel electronic, optical, or magnetic properties. Integrated circuits obtained with this approach of molecular-level control of material composition and structure may lead to devices and fabrication strategies not possible with top-down methods (Amarchand Satyapalan et al., 2005). The field of self-assembled monolayers (SAMs), especially mono and multilayer assemblies of organic materials on various substrates has been most extensively studied in recent years. The compelling force for this research is the importance of such formations to nanoelectronic device fabrication, for modifying the surface wetting/adhesion properties, for sensor applications and for corrosion resistance and molecular electronics (Kaushik Nayak et al. 2007). With the limitations in lithography techniques, to get features smaller than 10 nm, the molecular self-assembly provides the route to both smaller features and lower costs. Because of the ability to form layers with atomic resolution thickness and spacing, they are used as ultra thin resists and passivating layers. CNTs, polyphenylenes, porphyrins and DNA strands are some of the molecules that are being actively researched for the above applications (Reimers et al., 1996). 7