Proceedings of the 2009 IEEE International Conference on Mechatronics. Málaga, Spain, April 2009. 978-1-4244-4195-2/09/$25.00 (c) 2009 IEEE Left to Right Serial Multiplier for Large Numbers on FPGA H.Bessalah, K.Messaoudi, M.Issad & N.Anane System Architecture & multimedia CDTA PB17, Baba Hassen Algiers, Algeria. Kmessaoudi@cdta.dz , kmessaoudi.khadi@gmail.com M.Anane National informatics institute INI Algiers, Algeria. m.anane@ini.dz Abstract— A new high precision serial multiplier with Most Significant Digit First (MSDF) is presented. This one uses a Borrow-Save (BS) adder to perform the reduction of large length partials products required by the multiplication of large numbers. The results are converted from BS form to the 2‘s complement representation by the on-the-fly conversion which let the conversion of the digit result as soon as it is obtained. It is shown that the comparison between the residual and these constants (-3/2, -1/2, 1/2 and 3/2) needed in the radix-2 on line multiplication, present problem in high precision computation. However, in the proposed method the operands are introduced digit by digit with MSDF mode and results are obtained in the same manner with fixed time delay independently of the operand size. So, this approach is advantageously used for the long multiplication computation. This method has been tested by the execution of a program developed with Maple 9.5 for several test vectors. The results of the implementation of this multiplier for several operands sizes (128,256, 512, and 1024) on Virtex-II FPGA Circuit confirm that the multiplication is performed in constant time. Keywords-component: Multiplication, On-line arithmetic, High precision, Architecture, VHDL, FPGA, Virtex-II. I. INTRODUCTION In the last two decades the focus of digital design has been primarily on computation performances, however the precision remained almost unchanged and limited to simple and double precision of IEEE-754 standard [1]. In addition, several scientific and technical computations are numerically intensive and require arithmetic operators with very high precision. A good example of this kind of operation is founded in cryptography [2], where with the constant growth of the data communications; the security becomes more and more an important characteristic. Encryption/Decryption data need arithmetic operators with very high precision about 200 to 2000 bits. Several fields can also be cited such as the electronic signatures, the medical imagery, the generation of random numbers, the reduction of fraction in infinite precision and other more critical applications such as the nuclear simulators of stations and the military batteries of air defense. Therefore, the calculation in high precision was the object of several works [3, 4, 5, 6], who clearly reveal the adaptation of the on-line arithmetic for this kind of calculation. Since, in the online arithmetic, the operands, as well as the results, flow serially through the computation in a digit by digit manner starting from the most significant digit (MSDF). The advantages of online arithmetic have been to permit the computation of all operations with MSDF mode which reduce the interconnection bandwidth between modules and allow parallelism between several operations. Moreover, to manipulate large numbers in parallel way presents always a hardware problem, because parallelism requires large processing circuits that must comprise several inputs-outputs pins according to the size of the operands, what increases circuitry complexity. Among these works, A.Guyot, Y.Herreros and J-M.Muller presented in [4] the implementation on VLSI of an online Multiplier /Divider for large numbers. Subsequently, Y.Hornik sustained in the same context in order to implement several online operators for high precision [5]. The drawback of these operators is that their architectures are proportional to the operand size, which generates a very important hardware. We can also cite the work of M.D.Ercegovac and A.F Tencas in [6], where they elaborate divider architecture in long precision while using the online mode for high radix. However, the use of the binary on-line arithmetic in high precision, presents generally a problem in the selection of the result digit. Since, the generation of this digit is done after the comparison between the residual noted by H[j], which is represented in redundant notation, and constants represented in 2’s complement. This comparison is possible only after the conversion of the total residual to 2’s complement. This requires the use of carry propagate adder depending on the operands size. Consequently the delay of generation of the digit result will be proportional to the time of this adder. Several works detailed in [7, 8, 9, 10] present solutions based on the overlapping of the selection intervals, thus the operation of comparison is carried out only on a fixed part of the residual. This part is deduced after the estimation of the residual to a value which contains only its significant digits.