SPARC16: A new compression approach for the SPARC architecture Leonardo Ecco, Bruno Lopes, Eduardo C. Xavier, Ricardo Pannain, Paulo Centoducatte, Rodolfo Azevedo Institute of Computing University of Campinas - UNICAMP Av. Albert Einstein, 1251, Campinas, Brazil leonardo.ecco@students.ic.unicamp.br, {bruno.lopes,ecx,pannain,ducatte,rodolfo}@ic.unicamp.br Abstract RISC processors can be used to face the ever increasing demand for performance required by embedded systems. Nevertheless, this solution comes with the cost of poor code density. Alternative encodings for instruction sets, such as MIPS16 and Thumb, represent an effective approach to deal with this drawback. This article proposes to apply a new encoding to the SPARCv8 architecture. Through extensive analysis of a program mix from the Mibench and Media- bench benchmark suites, we suggest a new 16-bit instruc- tion set, easily translated to its 32-bit counterpart during execution time. Using the aforementioned program mix to infer how code could be represented in the proposed 16-bit ISA, compression ratios as low as 56% can be obtained. We also evaluated the cache behavior and showed reductions of 42% on cache misses that can increase performance up to 28% (for patricia program with 2KB cache). 1 Introduction Recent works in the Code Compression area have proved that code size reduction is not only a matter of reducing the program footprint on memory but also a very effective way to improve the program performance while reducing the total power on a system [4, 8, 18]. Going further, it is not only necessary to have good algorithms to encode the program instructions but also a very good decompression system to allow all these gains together. The Code Compression problem can be stated as the search for an alternative representation to the program in- structions that reduces the memory usage and can be done both in software and hardware [3], usually with different goals. While the software approach focuses on the max- imum reduction on the program size, at the possible cost of program performance since the decompression will be done in software, the hardware approach focuses on decom- pression speed, usually at the cost of code size reduction. There are, basically, two different approaches for hardware decompression, one that compresses instructions or blocks of the program in an ad-hoc manner, and another that tries to create an alternative encoding for the instructions in a smaller size, like representing the 32-bit instructions in a well-defined 16-bit format. This paper focuses on the latter approach to find a new encoding to the SPARC ISA. The SPARC ISA was selected after an analysis of 15 variations of 7 different ISAs and represent a good trade- off between opportunity to compress (big code size) and impact of the result (the SPARC ISA still has a good user base nowadays). In this work, we will use the term Compression Ratio to represent the code size reduction. Equation 1 shows how the Compression Ratio should be calculated. It is important to notice that, in this case, lower means better. A Com- pression Ratio of 56% means that the program is reduced to 56%. In this number, all the overhead should be included. Unfortunately, not all related work in the area consider the overhead in this number. Compression Ratio = Compressed Size + Overhead Original Size (1) We used the MediaBench and MiBench benchmarks to analyze the instruction occurrences and design the SPARC16 encoding. The results were evaluated using the same programs from MediaBench (average 58.1%, better 56.4%), MiBench (average 57.6%, better 56.4%), and with the Linux Kernel (64.4%) and binaries (64.2%). We also evaluated the instruction cache behavior of these programs and found that it is possible to reduce the miss rate in 42% which can improve the performance (28% on the instruc- tion cache in the patricia program) and reduce the power consumption. This paper is organized as follows: Section 2 describes