Delivered by Ingenta to University of Kentucky Libraries (cid 57004677), University of Kentucky (cid 70025377), University of Kentucky (cid 292596), University of Kentucky Libraries (cid 1058) IP : 127.0.0.1 Thu, 01 Sep 2005 13:17:18 COMMUNICATION Copyright © 2005 American Scientific Publishers All rights reserved Printed in the United States of America Journal of Nanoscience and Nanotechnology Vol. 5, 1745–1748, 2005 Fabrication of a One-Dimensional Array of Nanopores Horizontally Aligned on a Si Substrate Hongguo Zhang, 1 Zhi Chen, 1 ∗ Tianxiang Li, 2 and Kozo Saito 2 1 Department of Electrical and Computer Engineering and Center for Nanoscale Science and Engineering, University of Kentucky, Lexington, KY 40506, USA 2 Department of Mechanical Engineering, University of Kentucky, Lexington, KY 40506, USA A one-dimensional array of nanopores horizontally aligned on a silicon substrate was successfully fabricatedbyanodicaluminumoxidation(AAO)usingamodifiedtwo-stepprocedure.SEMpictures show clear nanostructures of well-aligned one-dimensional nanopore arrays without cracks at the interfaces of the sandwiched structures. The processes are compatible with the planar silicon inte- grated circuit processing technology, promising for applications in nanoelectronics. The formation mechanism of a single nanopore array on Si substrates was also discussed. Keywords: Nanopore Arrays, Anodization, AAO, 1-D Array, Nanotemplate. In the past decade, as an effective self-assembly template, nanoscale anodic aluminum oxide (AAO) has attracted much interest for fundamental scientific research as well as industrial applications due to the high aspect ratio (∼1000), high pore density (∼10 11 pores/cm 2 , high level of ordering and uniformity. 1–6 It is a very simple and facile approach because AAO templates are well-defined and their lengths and diameters are easily controlled. If the AAO template fabrication can be integrated into the mature Si integrated circuit processing technologies, it will be more useful for fabrication of nanoscale electronic devices. Up to now, it is still very difficult to utilize these AAO templates for fabrication of nanoelectronic devices, because all the AAO templates were vertically grown in two-dimensions (2-D) on substrates, not compatible with the mainstream Si planar processing technology. If a one- dimensional (1-D) AAO array with nanopores horizontally aligned on a Si substrate can be formed, it will be much more promising for fabrication of nanoelectronic devices and nano-electromechanical systems (NEMS) using the planar processing technology. Although another material, mesoporous silica with a sub-10 nm pore structure, shows promising as a self-organized template, 7–9 it is still very difficult to fabricate a single array of nanopore chan- nels using mesoporous silica. Masuda et al. 10 attempted ∗ Author to whom correspondence should be addressed. fabrication of 1-D AAO templates using a sandwiched structure on a glass substrate (Al 2 O 3 /Al/Glass). However, they have only achieved very limited success, because no follow-up research has ever been carried out and the pore structures are hardly distinguishable in their scanning elec- tron microscope (SEM) pictures. 10 In addition, in their process, the Al 2 O 3 film and glass substrates were used, which are not compatible with the silicon integrated circuit processes. We attempted to improve their process so that it may be compatible with the Si integrated circuit processes. We found that the major difficulty for realization of the 1-D AAO nanopore array using conventional anodization was the cracks occurring at the interface between the SiO 2 and the AAO layer. The presence of cracks suggests that this approach is unreliable and substantial improvement is needed. This might be why it is hard to view Masuda’s SEM images. In this communication, we will present successful fabrication of horizontal 1-D AAO templates without any cracks at the two interfaces using a modi- fied two-step process, based on two types of structures, SiO 2 /Al/SiO 2 /Si and SiO 2 /Al/Si. The fabrication processes are completely compatible with the Si integrated circuit processes. The fabrication processes of the two structures, SiO 2 /Al/ SiO 2 /Si and SiO 2 /Al/Si, are illustrated schematically in Figure 1. First, For the SiO 2 /Al/SiO 2 /Si structure, a 100-nm layer of SiO 2 was thermally grown on an undoped J. Nanosci. Nanotech. 2005, Vol. 5, No. 10 1533-4880/2005/5/1745/004 doi:10.1166/jnn.2005.157 1745