Abstract On-chip memories can consume multiple times the area of a processor core, thus affecting to the chip costs dramatically. In this paper, three approaches for reducing program memory footprint in a DSP processor are analyzed: fully 16-bit and two versions of mixed 16/32-bit instruction encodings. A separate decompression logic is implemented between memory and core, so the 32-bit processor core is remained unchanged. Compared to the original 32-bit instruction set, the fully 16-bit ISA (Instruction Set Architecture) eliminates 22% of the program memory footprint with a 1.55 times the original runtime. Mixed 16/32-bit ISAs achieve virtually same memory size, but with a faster runtime of 1.29 times the original at best. 1. Introduction The chip size is often a dominating design aspect in modern electronics, especially with consumer electronics chips in mass production. One major contributor to the chip area are on-chip memories which can consume many times the area of the processor core itself. Program memory size can be reduced by shortening instruction word length. The simplest way to realize this is to fit all the instructions to a shorter pattern, as proposed in [1] for RISC processors. However, this makes it more difficult to handle long addresses or constants and increases execution time. Therefore some kind of combination of instructions of different lengths might be better, like ARM 7TDMI 16/32 -bit ISA for RISC processors [2]. In further optimizations also advanced code compression, code libraries, etc., could be used [3]. This paper presents three approaches for modifying a 32-bit instruction set of a DSP processor. The main goal is to reduce the program memory size with no changes to the earlier designed blocks (core, buses, I/O-devices, etc.). Different approaches are evaluated through an MPEG3 audio decoder implementation. The required hardware is presented and future work described at the end of the paper. 2. Instruction Set Encoding Schemes The processor which was used as a reference design is a parametrizable VS_DSP2 processor with instruction word of 32 bits [4]. The processor core is to remain untouched, so the shortened instructions are expanded to 32-bit with a separate decoding logic before forwarding them to the core. Conceptual floorplan of the chip with the decoding block included is presented in Fig. 1. 2.1 16-bit Instruction Set The easiest way minimizing the program memory size was to encode all instructions as 16-bit. This was realized by removing parallel moves included in the original ALU instructions and shortening address and constant fields of the control code. However, short jump addresses make the Figure 1: Conceptual floorplan of the VS_DSP2 processor chip, including the decompression hardware block. Advanced Instruction Set Architectures for Reducing Program Memory Usage in a DSP Processor Piia Simonen, Ilkka Saastamoinen, Mika Kuulusa and Jari Nurmi Institute of Digital and Computer Systems, Tampere University of Technology P.O. Box 553, FIN-33101 Tampere, Finland E-mail: piia.simonen@tut.fi Tel. +358 3 3115 4354, Fax. +358 3 3115 3095 Proceedings of the First IEEE International Workshop on Electronic Design, Test and Applications (DELTA02) 0-7695-1453-7/02 $17.00 ' 2002 IEEE