Multiple voltage and frequency scheduling for power minimization Venkatesan Muthukumar * , Bharath Radhakrishnan, Henry Selvaraj Department of Electrical and Computer Engineering, University of Nevada Las Vegas, 4505 Maryland Parway, P.O. Box 4026, Las Vegas NV 89154, USA Received 15 March 2003; received in revised form 5 February 2004; accepted 1 July 2004 Available online 23 December 2004 Abstract The design description for an integrated circuit may be described in terms of three domains, namely: (1) behavioral domain, (2) structural domain and (3) physical domain. These domains may be hierarchically divided into several levels of abstraction. Classically, these level of abstraction are (1) Architectural or Functional level, (2) Register-transfer level, (3) Logic level and (4) Circuit level. Some of the design problems associated with VLSI circuit design are area, speed, reliability and power consumption. With the development of portable devices, power consumption has become a dom- inant design consideration in the modern VLSI design area. In each of these domains there are a number of design chal- lenges to reduce power. For instance, at the behavioral level, the freedom to choose multiple voltages and frequencies to minimize power to meet the given hard time constraints is considered as an active field of research to minimize power. Various past researches have showed that higher the level of abstraction, better the ability to address the problems asso- ciated with the design. Therefore this work proposes an algorithm that allocates both voltage and frequency simulta- neously to the operations of the directed flow graph to optimize power given the time constraints. The resources required for multiple voltage-frequency scheduling is derived using the classical force directed scheduling algorithm. This algorithm has been implemented and tested on High-Level synthesis benchmarks for both non-pipelined and pipe- line instances. Ó 2004 Elsevier B.V. All rights reserved. Keywords: Embedded system; Scheduling; Mutiple voltage and frequency scheduling 1. Introduction High-Level Synthesis (HLS) is the process of translation of a behavioral description of a system into a structural description that consists of a set 1383-7621/$ - see front matter Ó 2004 Elsevier B.V. All rights reserved. doi:10.1016/j.sysarc.2004.07.005 * Corresponding author. Tel./fax: +1 702 895 3566. E-mail address: venkim@egr.unlv.edu (V. Muthukumar). Journal of Systems Architecture 51 (2005) 382–394 www.elsevier.com/locate/sysarc