Novel gate and substrate triggering techniques for deep sub-micron ESD protection devices O. Semenov a, * , H. Sarbishaei a , V. Axelrad b , M. Sachdev a a Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, Ont, Canada N2L 3G1 b Sequoia Design Systems, 137 Chapman Rd., Woodside, CA 94062, USA Received 13 May 2005; received in revised form 26 July 2005; accepted 27 July 2005 Available online 12 September 2005 Abstract As technology feature size is reduced, ESD becomes the dominant failure mode due to lower gate oxide breakdown voltage. In this paper, the effectiveness of new gate and substrate triggering techniques has been investigated to lower the trigger voltage of the LVTSCR and MOSFET based ESD protection circuits using 2D simulations and HBM/TLP measurements. The simulation results show that the using these techniques reduces the ESD triggering voltage by 63 and 44% for MOSFET-based and LVTSCR-based ESD structures, respectively, under 2 kV HBM ESD stress. The effectiveness of proposed gate and substrate triggering techniques is also confirmed by the HBM and TLP measurements. q 2005 Elsevier Ltd. All rights reserved. Keywords: Electrostatic discharge (ESD); Gate triggering; Substrate triggering; ESD robustness 1. Introduction Electrostatic discharge is considered as a major reliability threat in the semiconductor industry for decades. It was reported that ESD and EOS are responsible for up to 70% of failures in IC technology [1]. Therefore, each I/O must be designed with a protection circuitry that creates a discharge path for ESD current. As a CMOS technology scales down, the design of ESD protection circuits becomes more challenging. This is due to thinner gate oxide and shallower junction depth in advanced technologies that makes them more vulnerable to ESD damages. In addition, advanced process techniques, such as silicidation, make ESD performance of protection devises even worse. While the physical dimensions of VLSI devices continue to shrink, the magnitude of the ESD event remains the same. To test the protection level of ESD devices, different standards are available. Human body model (HBM) and Charged device model (CDM) are more common. The required protection level depends on application and is usually at least 2 kV for HBM and 500 V for CDM. MOSFETs and silicon-controlled rectifiers (SCRs) are the two popular protection elements that are used in industry [2]. These devices are generally used in gate-grounded- NMOSFET (GG-NMOSFET) and low voltage triggered SCR (LVTSCR) configurations. There are some practical issues related to each of them. GG-MOSFET is usually realized using multiple fingers. In order to obtain maximum protection and avoid current filamentation and thermal runaway [3], all fingers should turn on at the same time. This can be achieved using gate coupling [4], substrate triggering [5] techniques or by applying layout technique, so-called Back-End-Ballast (BEB) poly resistors in compact Merged- Ballast-Circuit (MBC) configurations [6]. In addition, these techniques reduce the first breakdown voltage of MOSFET and further increase the protection level of the MOSFET. Chen et al. explained the operation principles of gate- grounded design, gate-driven design, and substrate trigger- ing design of CMOS devices for ESD protection using energy-band diagrams [7]. On the other hand, the conventional LVTSCR has the first breakdown voltage, which is not low enough to ensure the required protection of a gate oxide in advanced CMOS technologies [8]. Microelectronics Journal 37 (2006) 526–533 www.elsevier.com/locate/mejo 0026-2692/$ - see front matter q 2005 Elsevier Ltd. All rights reserved. doi:10.1016/j.mejo.2005.07.019 * Corresponding author. Address: Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, Ont., Canada N2L 3G1. Fax: C1 519 746 3077. E-mail address: osemenov@vlsi.uwaterloo.ca (O. Semenov).