Conduction Bottleneck in Silicon Nanochain Single Electron Transistors Operating at Room Temperature Muhammad A. Rafiq 1;6;7 , Katsunori Masubuchi 1 , Zahid A. K. Durrani 2;6 , Alan Colli 3 , Hiroshi Mizuta 4;6 , William I. Milne 5;6 , and Shunri Oda 1;6 1 Quantum Nanoelectronics Research Centre, Tokyo Institute of Technology, Meguro, Tokyo 152-8552, Japan 2 Department of Electrical and Electronic Engineering, Imperial College London, South Kensington Campus, London SW7 2AZ, U.K. 3 Nokia Research Centre c/o Nanoscience Centre, Cambridge CB30FF, U.K. 4 Nanoscale Systems Integration Group, School of Electronics and Computer Science, University of Southampton, Southampton, SO17 1BJ, U.K. 5 Engineering Department, University of Cambridge, Cambridge CB3 0FA, U.K. 6 SORST JST (Japan Science and Technology Agency), Kawaguchi, Saitama 332-0012, Japan 7 Department of Chemical and Materials Engineering, Pakistan Institute of Engineering and Applied Sciences, 45650 Islamabad, Pakistan Received October 31, 2011; accepted December 10, 2011; published online February 6, 2012 Single electron transistors are fabricated on single Si nanochains, synthesised by thermal evaporation of SiO solid sources. The nanochains consist of one-dimensional arrays of 10 nm Si nanocrystals, separated by SiO 2 regions. At 300 K, strong Coulomb staircases are seen in the drain–source current–voltage (I ds –V ds ) characteristics, and single-electron oscillations are seen in the drain–source current–gate voltage (I ds –V gs ) characteristics. From 300–20 K, a large increase in the Coulomb blockade region is observed. The characteristics are explained using single- electron Monte Carlo simulation, where an inhomogeneous multiple tunnel junction represents a nanochain. Any reduction in capacitance at a nanocrystal well within the nanochain creates a conduction ‘‘bottleneck’’, suppressing current at low voltage and improving the Coulomb staircase. The single-electron charging energy at such an island can be very high, 20k B T at 300 K. # 2012 The Japan Society of Applied Physics 1. Introduction Single-electron devices in silicon, where charge on a nanoscale ‘‘island’’ is controlled at the one-electron level using the ‘‘Coulomb blockade’’ effect, 1–15) are highly promising systems for the development of low electron number, low power, transistor and memory large-scale integrated (LSI) circuits. 16,17) The single electron transistors have also been fabricated in materials other than Si. 18,19) Practical application of these devices requires room temperature operation and therefore a large island single- electron charging energy E c ¼ e 2 =2C  k B T ¼ 26 meV, where C is the total island capacitance and temperature T ¼ 300 K. In practice, this requires C  1 aF or less and island dimensions <10 nm, such that the island forms a quantum dot. Room-temperature single-electron transistors (SETs) with islands of this scale have been fabricated mainly using high-resolution electron beam (e-beam) lithogra- phy. 20,21) These include both single-island, double-tunnel junction 20,22,23) and many island, multiple tunnel junctions (MTJ) devices. 21) Recent measurements on SETs with ultra- small islands, with diameter down to 2 nm, show room- temperature single-electron oscillations in the drain–source current–gate voltage (I ds –V gs ) characteristics with very large peak–valley ratios, 100 or greater. 23–25) However, a ‘‘Coulomb staircase’’ 1) in the drain–source current–voltage (I ds –V ds ) characteristics can be less well resolved. The devices may be defined by complex high-resolution lithography 20–23) or alternatively, defined ‘‘naturally’’ by material growth techniques. Examples of the later approach include SETs fabricated using nanocrystalline Si thin films, where crystalline Si grains 10{30 nm in diameter form charging islands. 18,24,26) These techniques raise the possi- bility of control over the island morphology at the nanoscale by controlling growth parameters. Recently, we have observed strong Coulomb staircases at room temperature in the MTJ formed by a single Si nanochain. 27) The Si nanochains, prepared by thermal evaporation of SiO solid sources, 28,29) consist of one- dimensional arrays of 10 nm diameter Si nanocrystals (SiNCs) separated by narrow SiO 2 regions. Here, the SiNCs form charging islands and the SiO 2 regions form tunnel barriers. Nanochain synthesis allows the preparation of very large ‘‘bulk’’ quantities of MTJs and Si quantum dots. In these MTJs, both islands and tunnel barriers are naturally- defined in entirety. Furthermore, in contrast with nanocrys- talline Si thin films, 18,24,25) variations in SiNC size and separation within the same nanochain are better controlled (16% variation). 27) Other investigations of these systems include measurement of electron tunneling in ensembles of Si nanochains using in situ scanning electron micros- copy, 30) non-gaussian fluctuations in charge transport in Si nanochains, 31) electrical breakdown of individual nano- chains, 32) and a theoretical prediction of negative differential conductance with large peak to valley ratio. 33) However, the detailed mechanism for single-electron effects in the nanochains, and the possibility of gate-control, is unclear. In this paper, we report the I ds –V ds and I ds –V gs char- acteristics of room-temperature SETs fabricated using single Si nanochains. At 300 K, strong Coulomb staircases with varying current step height are seen in the I ds –V ds char- acteristics, and single-electron oscillations are seen in the I ds –V gs characteristics. The temperature dependence of the Coulomb staircase from 300–20 K shows a large increase in the width of the Coulomb blockade region. The new experimental data sets presented here that were not present in ref. 27 consist of a temperature dependence of the I ds –V ds curves, arrhenius curve and single electron oscillations. We investigate these characteristics using single-electron Monte Carlo simulations of an MTJ where the gate capacitance C g at the islands is significant compared to the tunnel junction capacitance C. Here, the effective capacitance C eff for islands within the MTJ is reduced due to the presence of the capacitive array on either side, strengthening the Coulomb staircase at 300 K. The corresponding single- electron charging energy can be very large, E c ¼ e 2 =2C eff  0:3 eV  11k B T at 300 K. Furthermore, we find that the Japanese Journal of Applied Physics 51 (2012) 025202 025202-1 # 2012 The Japan Society of Applied Physics REGULAR PAPER DOI: 10.1143/JJAP.51.025202