FirmLeak: A framework for efficient and accurate runtime estimation of leakage power by firmware Arun Joseph, Anand Haridass, Charles Lefurgy + , Spandana Rachamalla, Sreekanth Pai, Diyanesh Chinnakkonda, Vidushi Goyal * IBM Systems & Technology Group, IBM Research + , IIT Kharagpur * arujosep@in.ibm.com Abstract— Separating the dynamic power and leakage power components from total microprocessor power can enable new optimizations for cloud computing. To this end, we introduce FirmLeak, a new framework that enables accurate, real-time estimation of microprocessor leakage power by system software. FirmLeak accounts for power-gating regions, per-core voltage domains, and manufacturing variation. We present an experimental evaluation of FirmLeak on a POWER7+ microprocessor for a range of hardware parts, voltages and temperatures. We discuss how this can be used in two applications to manage power by 1) improving billing of energy for cloud computing and 2) optimizing fan power consumption. I. INTRODUCTION Power consumption continues to be major concern that impacts design constraints such as reliability, thermal margins and cost for data centers and enterprise servers [1]. The contribution of leakage power to total power consumption is quite significant [2, 3, 4]. Some power management optimizations focus primarily on the leakage power component of the total power [5]. Therefore, it is valuable to estimate the leakage power apart from the total power. Runtime power management in system firmware depends on accurate, real- time power consumption sensors. The leakage power estimation in modern high-performance many-core microprocessors, must account for significant manufacturing variation (core-core and chip-chip) [6] as well as workload- induced temperature variation across cores. The introduction of on-chip voltage regulators means that cores may operate at unique voltages which will cause leakage to vary widely from core to core. Additionally, the ability to power-gate entire cores is becoming common [7]. More recently, fine-grained runtime power gating (RTPG) has been effectively adopted even for the different functional units in a processor [8, 9]. Since firmware power management may operate on a longer time intervals than power-gating of cores or function units, the ability to derate the leakage estimate to account for the actual power-on time becomes important. A. Prior Work There is some amount of prior academic and industrial work which provides solutions for runtime estimation of leakage power. Wei et al. [5] proposed an equation for estimating POWER7+ [10] VDD leakage power. Ibrahim et al. [11] proposed the use of leakage power tables, indexed by voltage and temperature, which are loaded at boot time. A driver loads the table depending on a leakage identifier and, the leakage power is estimated from the measured runtime voltage and temperature. Monferrer et al. [12] proposed the use of real- time voltage, temperature, and pre-determined constants to Process, Voltage, Temperature (PVT) independent Leakage Abstract Generation PVT independent Power Gating Domain Leakage Abstract Table Process Corner from Manufacturing Test EPROM Hardware SoC Microcontroller FirmTech Leakage Power API Firmware Other FW Silicon Voltage & Temperature Measurements Processor Process, Voltage, Temperature (PVT) independent Leakage Abstract Generation PVT independent Power Gating Domain Leakage Abstract Table Process Corner from Manufacturing Test EPROM Hardware SoC Microcontroller FirmTech Leakage Power API Firmware Other FW Silicon Voltage & Temperature Measurements Processor Fig. 1. FirmLeak Overview compute leakage power from a base reference leakage power value. Accurate runtime estimation of leakage power from [5, 11] requires a very intensive (for each unique hardware part or component, and across a wide voltage and temperature operation ranges) post-silicon leakage power characterization and data collection exercise. Considering the amount of variation in newer technology nodes [6], and the notable cost involved in tester time, this is a significant overhead on the post-silicon power characterization, power management and product teams, and often late in product cycle. Prior approaches [5, 12] do not accurately account for the notable real-time response variations and relative changes in the leakage power contributions of the different device types that were used in the design of the processor, under varying conditions of process, voltages and temperatures. Also, many prior techniques do not provide efficient techniques for real-time estimates of processor power gating domain leakage power. B. FirmLeak In this paper, to overcome the above limitations of prior approaches, we introduce FirmLeak, a new framework for efficient runtime estimation of leakage power by firmware. Fig.1. shows a high-level overview of FirmLeak. FirmLeak introduces the use of Process, Voltage and Temperature (PVT) independent pre-silicon Power Gating domain Leakage Abstracts (PGLA) in firmware to accurately estimate per- device type contributions and total runtime leakage power. A Technology-specific Leakage power estimation Software (TLS) module, residing in firmware, reads the different PGLAs, along with real-time voltage and temperature information from on-chip hardware sensors, to enable efficient runtime estimation of leakage power. Process corner information learned from manufacturing test procedures, which 2015 28th International Conference on VLSI Design 1063-9667/15 $31.00 © 2015 IEEE DOI 10.1109/VLSID.2015.84 464 2015 28th International Conference on VLSI Design and 2015 14th International Conference on Embedded Systems 1063-9667/15 $31.00 © 2015 IEEE DOI 10.1109/VLSID.2015.84 464