Microelectron. Reliab., Vol. 31, No. 2/3, pp. 271-276, 1991. 0026--2714/9153.00+ .00 Printed in Great Britain. © 1991 PergamonPressplc OPTIMIZATION OF TEST PARALLELISM WITH LIMITED HARDWARE OVERHEAD SHENG FENG and YASHWANTK. MALAIYA Computer Science Department, Colorado State University, Fort Collins, CO 80523, U.S.A. (Received for publication 22 May 1990) Abstract--The main considerations for built-in self-test (BIST) for complex circuits are fault coverage, test time, and hardware overhead. In the BIST technique, exhaustive or pseudo-exhaustive testing is used to test the combinational logic in a register sandwich. If register sandwiches can be identified in a complex digitial system, it is possible to test several of them in parallel using the built-in logic block observation (BILBO) technique. Concurrent built-in logic block observation (CBILBO) technique can further improve the test time, but it requires significant hardware overhead. A systematic scheduling technique is suggested to optimize parallel tests of register sandwiches. Techniques are proposed to deal with shared registers for parallel testing. The proposed method attempts to reduce further the test time while only modestly increasing the hardware overhead. 1. INTRODUCTION Design for testability (DFT) incorporates extra circuitry into the unit under test during the initial design so that test cost is reduced. The test cost includes (1) the cost of generating test patterns, (2) the cost of test equipment, (3) the hardware overhead, and (4) the test time. One of the major DFT techniques is built-in self-test (BIST) [1]. BIST significantly reduces the cost of test generation and can limit the use of expensive test equipment. This paper focuses on the test time and hardware overhead associated with BIST. Two major techniques, block level test scheduling, proposed by Kime and Saluja [2], Jone et al. [3], and Craig et al. [4], and step level test scheduling, proposed by Abadir and Breuer [5], can be used to improve the test time. The block level test scheduling proposed in [2, 4] considers a sequential machine as consisting of blocks. The blocks that can be tested simultaneously are called parallel test blocks. A sys- tematic way is suggested to obtain parallel test blocks such that the test time is reduced. Another block level test scheduling is introduced in [3]. The parallel test set and concurrent test set that are derived from the circuit under test are used to con- struct a binary compatibility tree so that some over- lying parallel test block sets, which can be tested with other sets, are identified. This improves the test time. The step level test scheduling exploits the parallelism of steps, applying test patterns to functional blocks. Sharing test pattern generator (TPG) and parallel signature analyzer (PSA) registers reduces hardware overhead. It is very efficient for pipelined architectures. The BILBO structure proposed by Konemann et al. [6] can be used either as a TPG or a PSA in different modes. A structure CBILBO with additional 271 hardware overhead was proposed by Wang and McCluskey [7]. CBILBO can be used as a TPG and a PSA at the same time, but nearly doubles the overhead. This paper presents a systematic schedule method- ology to find sets of parallel test register sandwiches [8] that can be tested in parallel. A systematic way to improve the BIST test time by making use of CBILBO is presented. The scheme keeps the hard- ware overhead minimal while attempting to reduce the overall self-testing time. 2. MOTIVATION AND DEFINITION A sequential machine is shown in Fig. 1. If BILBO registers are used for R1, R2, and R3, CLB1, CLB2, and CLB3 could be tested serially. Blocks CLB1 and CLB2 can be tested in parallel if a CBILBO register replaces the BILBO register R2. CLB1 and CLB3 can be tested in parallel if R1 and R3 are CBILBO registers. CLB1, CLB2, and CLB3 can be tested in parallel if CBILBO registers are used for R1, R2, and R3. Let test times of CLB1, CLB2, and CLB3 by T1, T2, and T3 respectively. The total test times for the above four options are listed in Table 1. It is assumed that T1 > T2 >> T3. The second option reduces the test time signifi- cantly by using only one CBILBO register (R3). The last two options also reduce the test time, but require more hardware overhead. Table 1. Options for machine in Fig. 1 Type RI, R2, R3 System test time 1 BILBO, BILBO, BILBO T1 + T2 + T3 2 BILBO, CBILBO, BILBO T1 + T3 3 CBILBO, BILBO, CBILBO T1 + T2 4 CBILBO, CBILBO, CBILBO T1