60 Today’s system designers frequently integrate commercial, off-the-shelf (COTS) components and software as part of a new sys- tem. Although such designs need thorough testing and validation, COTS components present engineers with intellectual property issues and limited abilities for test and valida- tion. Often, COTS components’ proprietary nature complicates the validation process by prohibiting designers from implementing a robust test and validation strategy. To preserve a vendor’s intellectual property, for example, the vendor often provides designers only a high-level model, which limits access to its internals. T his may render the designer’s exist- ing simulation tools inadequate. In current approaches or methods to simu- late design environments that include both gate-level and behavioral models, designers resort to using a variety of tools and simula- tors. Often these simulators are “glued” together to accommodate different portions of a design, resulting in complex interfaces with high overhead, and impaired observation and accuracy. 1,2 An efficient and flexible approach to vali- dating designs that incorporate disparate COTS components is multilevel concurrent simulation. MCS is a research simulation tool developed in conjunction with Compaq Computer Corporation and Draper Labora- tories. MCS overcomes limitations imposed by merged simulator approaches. MCS achieves this by incorporating techniques that are not specific to any abstraction level, mak- ing it attractive for testing interface intercon- nects and mixed-mode logic. In this article we describe our approach, which is a cohesive simulator platform based on concurrent sim- ulation algorithms. Multilevel concurrent simulation Researchers have previously developed mul- tilevel simulation approaches, as explained in the “Multilevel simulation: Earlier work” box. However, many of these approaches— unlike ours— trade off speed for accuracy. We based our multilevel concurrent simulation approach on concurrent fault simulation algo- rithms and on the function list concept from Creator, a proven concurrent fault simulator. 1,3 MCS then extends these concepts with mul- tilevel modeling. Concurrent fault simulation, known for its efficiency in gate-level simulation, is one of the few techniques that can address accurate timing models, asynchronous circuits, and multilevel descriptions. 1 Furthermore, the Karen Panetta Lentz Jamie Heller Tufts University Pier Luca M ontessoro University of Udine THE VERIFICATION OF M ULTILEVEL DESIGNS, IN A SINGLE SIM ULATOR ENVIRONM ENT , CAN BE ACHIEVED EFFICIENTLY USING CONCURRENT SIM ULATION. 0272-1732/99/$10.00  1999 IEEE S YSTEM V ERIFICATION U SING M ULTILEVEL C ONCURRENT S IM ULATION .