Uniform ZnO Thin-Film Transistors by an Ambient Process Shelby F. Nelson, David Levy, Diane Freeman, Peter Cowdery-Corvan, Lee Tutt, Mitchell Burberry, Lyn Irving Eastman Kodak Company, 1999 Lake Avenue, Rochester NY 14650 USA Phone: 585-477-8417. E-mail: Y Backplane technologies for liquid crystal displays are well established and successful, and most current research in that area is conducted towards reducing costs. Backplanes for OLEDs, on the other hand, have yet to reach the overwhelming success in performance and yield enjoyed by the LCD industry. Of the prominent competing semiconductors for OLED backplanes, amorphous silicon has the drawback of low mobility ( 1 cm2/Vs) and threshold voltage variation upon bias stress [1], while low-temperature polysilicon struggles with achieving adequate threshold uniformity across a display backplane. One approach to solving these issues is to consider material sets other than silicon. We have fabricated zinc oxide thin-film transistors using a novel ambient deposition process, with maximum temperature of 200°C. The TFTs deposited this way show sufficiently good properties to make them potentially applicable to OLED display backplanes. The deposition system uses a proprietary process that operates in an open environment, i.e. requiring no containment chamber. This allows for a small footprint and an easy translation to a continuous roll-to-roll process. Typical deposition rates under the head are near 200 A/min. The TFTs presented here are grown on glass substrates coated uniformly with a gate conductor. The gate conductors are usually ITO (commercially available), but can be metals such as chromium or molybdenum. Both the gate dielectric and the semiconductor layer were coated using Kodak's apparatus. The gate dielectric was formed with Trimethylaluminum as an aluminum source and water as an oxidizer to produce aluminum oxide. The semiconductor was produced using diethylzinc as a zinc source and water as an oxidizer to produce zinc oxide. Aluminum source-drain contacts, patterned by shadow mask or lithographically, are thermally evaporated, with a width of 600 ptm and a length ranging from 50 to 150 pim. The semiconductor was isolated in each TFT by a simple photolithographic process. Normally no passivation layer is applied. With 100-nm-thick alumina gate dielectric, devices typically have saturation mobility above 10 cm2/Vs, and threshold voltage of between 6 and 7 V, subthreshold swing of 0.5 V/decade, and on/off ratio of 108. The gate leakage is less than 100 pA at 30 V, and because the leakage is over the entire 0.4 mm2 isolation patch of ZnO, it translates to a gate leakage current density of 2.5x10-8 A/cm2. The devices show good linear characteristics, with the linear mobility extracted at drain voltage of 0.1 V matching the saturation mobility. This suggests that there is negligible contact resistance. The uniformity of TFTs over the deposited area of 3 cm x 5 cm is tested on a large array of TFTs. For a typical example, the mobility is 15 + 2 cm2/Vs, the threshold voltage is 6.55 + 0.24 V, and the hysteresis, measured in the steep portion of the transfer curve, is 0.1 + 0.1 V. When carefully processed, the threshold voltage variation over the growth area can be less than 0.1 V. We have also tested the stability of these devices. Short tests of "shelf life," in which the sample is tested, exposed to room air and light, and retested after six months, showed the repeated measurements were well within the error bars of the initial measurements. A harsher test, of course, is a bias stress test. Devices were tested periodically while being stressed with gate bias of 20 V and drain bias of 10 V. Over an 18 h test, shifts as low as 1 V in threshold have been measured. This robustness to bias stress is critical for uncomplicated display pixel designs. However, not all our samples show equally good behavior, and the variables contributing to this are being explored. In summary, we have shown promising early data on the electrical performance of ambient-deposited ZnO. The novel deposition process uses a maximum temperature of 200°C, and is capable of producing TFTs with mobility, threshold uniformity, and bias stability values compatible with OLED backplanes. [1] M. J. Powell, IEEE Trans. Electron Dev., "The physics of amorphous-silicon thin-film transistors," vol. 36(12), p. 2753 (1989). 1-4244-11 02-5/07/$25.00 ©2007 IEEE 1 3