Micropower Two-Stage Amplifier Employing Recycling Current-Buffer Miller Compensation Wei Wang, Zushu Yan, Pui-In Mak, Man-Kay Law and Rui P. Martins 1 State-Key Laboratory of Analog and Mixed-Signal VLSI, University of Macau, Macao, China 1 – on leave from Instituto Superior Técnico, U of Lisbon, Portugal {E-mail Contact: pimak@umac.mo} Abstract—Proposed is a two-stage amplifier exploiting recycling current-buffer Miller compensation (CBMC). By reusing the most current-consuming devices in the 1 st stage as current buffer, such an amplifier not only can preserve the merits of typical CBMC implementation in creating the beneficial left-half-plane (LHP) zero, but also can avoid the drawbacks of typical CBMC scheme from degrading the power efficiency, DC gain, dc offset and noise performances. Optimized in 0.18μm CMOS via a low- power design procedure, the amplifier achieves >90dB DC gain, 4.5MHz unity-gain frequency and 57.2° phase margin at a 100pF capacitive load. The average slew rate and 1% settling time are 2.68V/μs and 0.239μs, respectively. The amplifier draws 22μA at a 1.2V supply. I. INTRODUCTION Two-stage amplifiers have underpinned a wide range of applications in analog circuits and subsystems due to its high DC gain and large output swing. The closed-loop stability is often secured via traditional Miller compensation (MC). The Miller capacitor, yet, induces a non-inverting feedforward signal path from the input of the 2 nd stage to its output, creating an undesirable right-half-plane (RHP) zero [1]. The RHP zero can be eliminated by using a voltage buffer, nulling resistor, or adding a transconductance stage to cancel the feedforward signal. However, the scheme based on current buffer, i.e. current-buffer Miller compensation (CBMC), offers more design freedom in optimizing the gain-bandwidth product (GBW), power and area, while enhancing the capacitive load (C L ) drivability [2]. CBMC also exhibits significant power supply rejection ratio (PSRR) improvement over that of MC [3]-[4]. Existing implementation of a two-stage CBMC amplifier invariably employs a PMOS input folded-cascode (FC) stage for its lower flicker noise, farther non-dominant pole and wider input common-mode level that can reach the ground, in comparison with its NMOS FC stage counterpart. The current buffer is either separately realized, or embedded in the FC stage, as shown in Fig. 1(a) and (b), respectively [5]. Yet, both have a number of drawbacks: the former [Fig. 1(a)] consisting of M 9a -M 11a suffers from increased offset voltage owing to the inevitable DC current mismatch between M 9a and M 11a . Replica biasing can alleviate the current mismatch [6], but it entails add-on bias circuitry and shows supply dependence. Another critical issue is the current buffer M 10a burns a large portion of power; as M 10a should generate at least 2x g m1a to guarantee reasonable stability margin [7], while g m1a is generally set high, for noise consideration. This leads to significant current drawn by M 10a and the output resistance reduction in the FC stage, degrading the DC gain and hence the dc offset performance. M 9a and M 10a also add parasitic capacitance penalizing the maximum attainable GBW. They and their biasing circuitry also contribute significant noise due to their large bias current and noise amplification. The latter [Fig. 1(b)] embodies the current buffer M 6b in the FC stage and avoid the mismatch problem and extra circuit overhead in Fig. 1(a). However, the removal of RHP zero is incomplete, even being placed higher than that in traditional MC [5]. Moreover, the left-half-plane (LHP) zero is far beyond that of Fig. 1(a), benefiting little to the phase margin (PM). Similarly, the issue of M 6b dominating the power of the FC stage has yet to be solved. Instead, M 5b drains the same amount of current as M 6b to balance the two folded branches, doubling the power budget. Thus, Fig. 1(b) is inferior to Fig. 1(a) in terms of power efficiency. This paper proposes a power-efficient recycling CBMC amplifier by recycling the most power-hungry devices in the FC stage as current buffer. The concise implementation not only inherits the advantages of both embodiments in Fig. 1 but also eliminates their drawbacks. Moreover, the proposed amplifier consumes less power and preserves a key LHP zero to benefit the PM, while being free from mismatch, extra auxiliary circuitry and gain reduction. A low-power design procedure is also described, which essentially leads to low power dissipation of the entire amplifier. V ip Vin V b1 V b2 VDD VSS V b4 V b3 V o C L V ip V in V b1 V b2 V b3 (a) (b) M1a M 2a M5a M 4a M3a M3b M4b M5b M 7a M6a M8a M1b M 2b M6b M 7b M8b M9b M10b M9a M10a M11a M12a M13a M0a M0b Cc Cc VDD VSS V o C L Fig. 1. Conventional two-stage CBMC amplifier implementations via: (a) a separate current buffer, and (b) an embedded one. 978-1-4799-3432-4/14/$31.00 ©2014 IEEE 1889