International Journal of Computer Applications (0975 – 8887) Volume 93 – No 10, May 2014 26 Design of Reversible Programmable Gate Array based on New Reversible Logic Modules Saleem M. R. Taha, Ph.D. Dept. of Electrical Engineering, College of Engineering, University of Baghdad, Jadiryah, Baghdad, Iraq ABSTRACT Reversible logic synthesis techniques will definitely be a necessary part of the long-term future of computing. The paper introduces the design of a new reversible logic module (RLM) with three versions I, II, and III. It is universal in two arguments. A proposed design of reversible programmable gate array (RPGA) based on the new (RLM) is presented. It is superior to previous types of (RPGA) structures in that the same type of reversible logic modules is used in the implementation of the entire circuit. Symmetric and no symmetric functions can be realized by the proposed (RPGA). Synthesizing reversibly the logic functions using this method is good for multi-output functions as well as it can be extended to incompletely specified functions. General Terms Design, Theory Keywords Reversible Logic Module, Reversible Logic Synthesis, RPGA 1. INTRODUCTION Interest in reversible logic started when Landauer (1961) proved that traditional binary irreversible gates lead to power dissipation in a circuit regardless of implementation [1]. Each bit of information that is lost, generates KT ln(2) Joules of heat energy, where K is Boltzmann’s constant and T the absolute temperature (Kelvins) at which computation is performed [2, 3]. Bennett (1973) showed that for power not to be dissipated in an arbitrary circuit, it is necessary that this circuit be built from reversible gates. The importance of Bennett’s theorem lies in the technological necessity that every future technology will have to use reversible gates in order to reduce power loss [4]. Reversible logic is an emerging research area. It has attracted significant attention in recent years. It has applications in quantum computing, nanotechnology, low power CMOS, optical computing, and DNA computing. Reversible technologies and the synthesis of reversible networks are potentially very promising areas of study with regard to further technological advances [5]. The high rate of power consumption and the emergence of quantum effects for highly dense ICs are the biggest problems in system design today and in the future. It is necessary to design reliable systems consuming as little power as possible and in which the signals are processed and transmitted at very high speeds with very high signal integrity. In order to reduce power consumption, physical processes have to be logically reversible. Reversible circuits are those circuits that do not lose information and reversible computation in a system can be performed only when the system comprises of reversible gates. These circuits can generate unique output vector from each input vector, and vice versa, that is, there is a one-to-one mapping (a permutation) between input and output vectors [6, 7]. Two constraints for reversible logic synthesis are: (1) feedback is not allowed, and (2) fan-out is not allowed (i.e., fan-out = 1). Reversible logic circuits have the same number of inputs and outputs. For an (n, k) function, i.e. function with n-input k-output, it is necessary to add inputs and/or outputs to make it reversible. “Garbage” is the number of outputs added to make an (n, k) function reversible. While the word “constant inputs” is used to denote the preset value inputs that were added to an (n, k) function to make it reversible. One of the important methodologies of reversible logic synthesis is the reversible programmable gate array (RPGA) method. This method is introduced in [8, 9]. It is based on regular structure to realize binary functions in reversible logic. This structure called a 2*2 Net structure, allows for efficient realization of symmetric functions. A regular structure means a logic circuit and its physical layout structure being an array of identical cells regularly connected, or a structure composed of few, regularly connected, structures of this type, called planes. By regularly connected, it is understood that every cell (except of boundary cells) is connected to its k neighbors. There is a subset of Boolean expressions that are specified as sum-of-products, in which every variable is either negated or not negated, but not both [9, 10]. The following three important definitions are mainly based on the topics described in [9]. Definition 1. The variable that stands non-negated (positive) throughout the expression is called a positive polarity variable. Variable that stands always in negated (negative) form is called a negative polarity variable. Definition 2. Unate function is a function expressed only using AND and OR operators in which every variable has either positive or negative polarity, but not both. Definition 3. Totally symmetric function that has value 1 when exactly k of its n inputs are equal 1 and exactly (n – k) remaining inputs are equal 0, is called a single-index symmetric function and denoted by S k (x 1 , x 2 , , x n ). Analogously, S {i, j, k} denotes the function that is 1 when i, j, or k of its variables are equal 1. The regular structure of RPGA has two regular planes (Figure 1, the Feynman gates are denoted as Feyn.). The first plane from left is planner, regular and algorithmically created (it is also called the triangular plane). It consists of OR/AND (MAX/MIN) combination cells, made up of (2, 2) reversible gates [8], to realize all positive unate symmetric functions (PUS) of its input variables. The second plane is just a sequence of columns of Feynman gates that converts these PUS functions to arbitrary symmetric functions at the bottom. Every output function is realized as an EXOR of PUS