Die-on-wafer and Wafer-level 3D Integration for Millimeter-Wave Smart Antenna Transceivers M.M. Hella, S. Devarajan, J.-Q. Lu, K. Rose and R.J. Gutmann Center for Integrated Electronics Rensselaer Polytechnic Institute, Troy, New York 12180, hellam@ecse.rpi.edu Abstract — A three-dimensional (3D) IC technology platform for high-performance, heterogeneous integration of silicon ICs for mm-wave smart antenna transceivers is presented. The platform uses dielectric adhesive bonding of fully-processed wafer-to-wafer aligned ICs, followed by a three-step thinning process and copper damascene patterning to form inter-wafer interconnects. A low noise amplifier (LNA), power amplifier (PA), and an analog-to- digital converter (ADC) are designed in RF-enhanced SiGe BiCMOS process to operate in the 24GHz ISM band. These critical design blocks serve as a step towards the realization of a complete system integrated with I/O matching networks, switches, antennas, and digital processing in a 3D configuration. I. INTRODUCTION The next wave of wireless communications seeks to improve data rates and channel capacity by employing larger bandwidths with higher efficiencies. One promising technology to attain this goal involves the use of smart- antenna technology whereby multiple antennas are combined intelligently at the transmitter and the receiver, both at the subscriber and the base station. Various forms of multiple antenna systems provide solutions for communications and radars, such as multiple-input- multiple-output (MIMO) diversity transceivers and synthetic aperture radars (SARs) [1]. The industrial, scientific, and medical (ISM) band at 24GHz is regarded as a potential candidate for such applications. Traditionally, communications systems working in the microwave/mm-wave band are realized using multiple microwave modules implemented mainly in GaAs, adding to overall cost and complexity. It is envisioned that single- chip silicon-based technologies will replace current solutions in a way similar to the trend that commercial cellular and PCS systems have taken for their implementation. System integration is the main key in the development of any low cost/high performance wireless networking system [2-3]. The major drive behind the 3D integration for mm-wave applications is the impact of interconnect losses at these frequencies (For example, the interconnect loss for a flip- chip packaged circuit is near 1.2dB at 60GHz [4]), together with the continuing demand for reconfigurable/smart silicon-based transceivers that interface with CMOS memory-intensive digital processors and possibly NMOS-based imagers. In this paper various issues related to the 3D integration for mm-wave transceivers will be addressed. The 3D technology platform is presented in section II. Some basic building blocks in the transceiver chain including a SiGe- based low noise amplifier ( LNA), a power amplifier (PA) and a high performance SiGe analog-to-digital converter (ADC) are introduced. II. 3D IC TECHNOLOGY PLATFORM Die-to-die, die-to-wafer and wafer-to-wafer approaches are in various stages of research and development [5]. Alternative wafer-to-wafer technology platforms are under development involving oxide-to-oxide bonding, copper-to-copper bonding, and dielectric adhesive bonding [5]. Our dielectric adhesive bonding approach accommodates wafer distortions and interface contaminants; in addition, a handling wafer is not required and wafers are thinned only after bonding to a host wafer. A three-wafer stack depicting our IC technology platform is shown in Figure 1(a) [6]. Fully processed wafers are aligned to within a micron after spin coating a micron thick benzocyclobutene (BCB) and soft baking the BCB to remove volatile components. The wafer pair is then bonded together in a bonder with a specified ambient, temperature and pressure cycle. After bonding, the top- Device surface Bond (Face-to-face) Bond (Face-to-face) 3rd 2nd 1st Plug Via Bridge Via Substrate Substrate Dielectric Dielectric Bond (Face-to-back) Device surface Device surface Substrate Multi-level on-chip interconnects Wafer Level Antenna and High Q Passives SiGe BiCMOS Transceiver, A/D CMOS Processor and Memory (b) (a) Fig. 1. (a) Schematic of a 3D integration platform, showing wafer bonding interface, vertical inter-wafer vias (plug- and bridge-type), and "face-to-face" and "face-to-back" bonding; (b) three-wafer/three-die stack for SiGe-based mm-wave transceiver.