FPGA and ASIC implementation of robust invisible binary image watermarking algorithm using connectivity preserving criteria P. Karthigaikumar a,n , K. Baskaran b,1 a Department of Electronics and Communication Engineering, Karunya University, Coimbatore, India b Department of Computer Science and Engineering, Government College of Technology, Coimbatore, India article info Article history: Received 14 December 2009 Received in revised form 20 August 2010 Accepted 23 August 2010 Available online 17 September 2010 Keywords: Watermarking FPGA ASIC Multimedia Low power VLSI abstract Digital watermarking is the process of hiding information into a digital signal to authenticate the contents of digital data. There are number of watermarking algorithm implemented in software and few in hardware. This paper discusses the implementation of robust invisible binary image watermarking algorithm in Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuits (ASIC) using connectivity preserving criteria. The algorithm is processed in spatial domain. The algorithm is prototyped in (i) XILINX FPGA (ii) 130 nm ASIC. The algorithm is tested in Virtex-E (xcv50e-8-cs144) FPGA and implemented in an ASIC. & 2010 Elsevier Ltd. All rights reserved. 1. Introduction In recent years, distribution of digital contents is one of the rapid up-coming fields owing to the latest progress in network and communication area, it is necessary to protect the data during transmission. Digital watermarking is a solution to the copyright [1] protection and authentication of data in the network. The data may be an image, audio, video, text or graphics [2,3]. In this paper binary image is given as input to the algorithm. The Watermark is included in the input signal to provide authentication and ownership to the transmitting signal. In general, any water- marking scheme consists of following parts, such as the water- mark, the encoder (insertion algorithm) and the decoder and comparator (verification or extraction or detection algorithm) [3,4]. The insertion algorithm inserts the watermark into the object, whereas the verification algorithm authenticates the object, determining both the owner and the integrity of the object. The watermarks can be applied either in spatial or in frequency domain (FFT, DCT [11] or wavelet). Even though spatial domain watermarking is less robust [5–7], the spatial domain schemes have less computational overhead compared with frequency domain schemes. The digital watermarks can be divided into four different types such as visible [7–10], invisible [7], robust and invisible fragile [12]. Each of the above watermarking domains is equally important due to its unique applications. There are numerous watermarking algorithms designed based on software and their implementa- tions are reported in the literature [13,14]. According to [28] only a few hardware schemes have been proposed. As proof of that, [27] provides list of the most watermarking hardware imple- mentations available in the current literature. Software implementation of watermarking algorithm has less useful when the image size and bit depth grow to high value. Hence hardware description languages are used to implement the media applications. Once the design has been programmed using VHDL and the desired performance is achieved, it can be downloaded into an FPGA. Digital revolution in video applications has brought profound challenges in media security and encryp- tion. Many techniques like including ownership protection, authentication, access control and annotation have been proposed to counter this challenge. Data hiding [26,29] is one of the technique to hide the secret data. It provides imperceptibility and robustness and has the ability to hide many bits. In the proposed watermarking technique, the pixels are flipped and hidden from the intruders. Reconfigurable techniques [8,30] can be applied to different blocks of processing element so that different image blocks can be watermarked in parallel. 2. Related research This section discusses the few hardware implementation of watermarking algorithms reported in the literature. The hardware Contents lists available at ScienceDirect journal homepage: www.elsevier.com/locate/mejo Microelectronics Journal 0026-2692/$ - see front matter & 2010 Elsevier Ltd. All rights reserved. doi:10.1016/j.mejo.2010.08.023 n Corresponding author. Tel.: + 91 94862 60288. E-mail addresses: Karthi_kumar_p@rediffmail.com (P. Karthigaikumar), baski_101@yahoo.com (K. Baskaran). 1 Tel.: + 91 9443661901 Microelectronics Journal 42 (2011) 82–88