International Journal of Computer Applications (0975 – 8887) Volume 122 – No.16, July 2015 14 Area Efficient Layout Design of CMOS Comparator using PTL Logic Jyoti ME Scholar Department of Electronics & Communication Engineering National Institute of Technical Teachers Training and Research, Chandigarh, India Rajesh Mehra, PhD Associate Professor Department of Electronics & Communication Engineering National Institute of Technical Teachers Training and Research, Chandigarh, India ABSTRACT Comparator is a very useful combinational logic circuit. In this paper performance analysis of CMOS Comparator and PTL logic design has been shown. In the design of integrated circuits, several logic families is being used which is described by Pass Transistor Logic (PTL). It reduces the count of transistors used to make different logic gates, by eliminating redundant transistors. The layout of 2-bit comparator is developed using automatic and semi-custom techniques. Both the layouts are compared and analyzed in terms of their area consumption. Automatic layout is generated from its equivalent schematic whereas semi-custom layout is optimized manually. The result shows that semi- custom layout of PTL logic consumes 35% less area as compared to CMOS logic design to provide area efficient solution. Keywords CMOS technology, Layout, Performance analysis, logic circuits, PTL 1. INTRODUCTION Comparator is a very useful combinational logic circuit & a basic arithmetic component of digital system. In many computers and other kinds of device processors, subtractors are used not only for the arithmetic calculations, but are also frequently used in other parts of the processor, where there is a requirement of calculating addresses, table indices, and similar operations[1]. Digital or Binary Comparators are made up from standard AND, NOR and NOT gates that compare the digital signals present at their input terminals and depending upon the condition of these inputs it produce an output. In Very Large Scale Integrated designs, Comparators are the common devices. In other words, in a given technology, transistors are required to compensate the reduction of supply voltage to achieve high speed, larger, which also means that more die area and power is needed [2]. For comparator with short input, this is suitable approach.The circuit complexity increases drastically for the comparator with longer inputs, accordingly operating speed is degraded. In the world of technology it has become essential to develop various new design methodologies to reduce the power and area consumption [3]. Most of the developed low-power SRAM techniques are used to reduce only read power. Since, in the SRAM cell, the write power is generally larger than read power. An SRAM cell is to reduce the power in write operation by introducing two tail Transistors in the pull-down path for reducing leakages [4]. Today leakage power has become an increasingly important issue in processor hardware and software design. With the main component of leakage, the sub-threshold current, exponentially increasing with decreasing device dimensions, leakage commands an ever increasing share in the processor power consumption [5]. Scaling down of the technology has led to increase in leakage current. Nowadays, a leakage power has become more dominant as compared to Dynamic power. Leakage current is a primary concern for low-power, high-performance digital CMOS circuits [6]. In one complete cycle of CMOS logic, current go from VDD to the load capacitance to charge it and then go from the charged load capacitance to ground during discharge. Due to this one complete charge/discharge cycle, a total of Q=CLVDD thus transferred from VDD to ground. Multiply by the switching frequency on the load capacitances to get the current used, and multiply by voltage [7]. In almost all digital processors, Comparator is a fundamental operation. In the last few years, a great deal of attention has received by the design of high-speed, low power, and area- efficient binary comparators since, as is well known, The examples of efficient architectures of binary comparators are demonstrated in [8]–[12]. In this paper, a comparative analysis about the Area and Power of different logic design of comparator has been presented. Furthermore, based on the comparator proposed in [13], a comparator is presented which consumes so much area and power on the other hand area can be reduced by making these circuit by semi custom technique. This modification results in considerably area efficient and power efficient when compared with the other one. 2-Bit Magnitude Comparator compares two numbers in which A0, A1, B0 and B1 are the two inputs and three outputs i.e A        and only one of the three outputs would be high accordingly if A is greater than or equal to or less than B. The truth table of 2-bit comparator with all possible combination is shown in Table 1 TABLE 1 Truth table of 2-bit comparator Input Output A1 A0 B1 B0 A A=B A 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0 0 1 0 0 0 1 0 0 1 1 0 0 1 0 1 0 0 1 0 0 0 1 0 1 0 1 0