Australian Journal of Basic and Applied Sciences, 6(7): 73-79, 2012 ISSN 1991-8178 Corresponding Author: Mohd Azfar Bin Tajul Arifin, Department of Electrical, Electronic and Systems Engineering, Universiti Kebangsaan Malaysia, 43600 Bangi, Selangor, Malaysia. E-mail: arifsobhan.bhuiyan@gmail.com 73 Design of A Low Power and Wide Band True Single-Phase Clock Frequency Divider Mohd Azfar Bin Tajul Arifin, Md. Mamun, Mohammad Arif Sobhan Bhuiyan, Hafizah Husain Department of Electrical, Electronic and Systems Engineering, Universiti Kebangsaan Malaysia, 43600 Bangi, Selangor, Malaysia. Abstract: The design of frequency synthesizer, often implemented by a phase-locked loop (PLL), is a challenging task for RF designers in terms of power dissipation. In this paper an ultra-low power wide band 2/3 prescaler simulated by CEDEC 0.18 μm CMOS technology is presented. The proposed prescaler is capable of operating up to 8 GHz with smooth output waveform for divide-by-2 operation. Compared with concurrent extended true single phase clock (E-TSPC) circuits at supply voltage of 1.8 V, more than 50% reduction in total power consumption is achieved for both divide-by-2 and divide- by-3 operations. It consumes 0.05 mW and 0.68 mW of power during divide-by-2 and divide-by-3 modes respectively. Key words: Frequency divider, Prescaler, True single-phase clock (TSPC), E-TSPC. INTRODUCTION In wireless communication systems, a phase-locked loop (PLL) is one of the main components for transceivers (Akter et al., 2008; Reaz et al., 2006; Mohd-Yasin et al., 2004). PLLs are mainly used for frequency synthesis to generate a local oscillator signal to up-conversion in the transmitter and down-conversion in the receiver. It is also used in producing high frequency oscillations in modern communication equipment (Marufuzzaman et al., 2010; Reaz et al., 2003; Zhang et al., 2011). The basic building blocks of a PLL are given in figure 1. A PLL is composed of a phase frequency detector (PFD) followed by an analog filter and a voltage- controlled oscillator (VCO). There is also a frequency divider (FD) or prescaler stage to be used as synthesizer feedback loop (Bazzazi and Nabavi, 2009; Gu et al, 2011). Fig. 1: Basic phase-lock loop (PLL) block diagram For a typical PLL, prescaler is used to generate a frequency that is a multiple of the reference frequency. In PLL loop as in Figure 1, the output of VCO is divided down by the FD. Then, the divided signal and TCXO are applied to the phase detector for comparison (Cheema et al, 2010). FD approach makes it easier to implement low power and offer smaller phase imbalance. FD can be categorized into three parts which are digital, analog and hybrid or combination of both. The digital part can be divided into static and dynamic FDs whereas the analog part consists of regenerative divider and injection locked FD. Hybrid of digital and analog divider only consists of travelling wave FD. True single-phase clock (TSPC) is under the dynamic sub-category of FD. The advantage of dynamic dividers over the others is reduced power consumption and less number of transistors. As in (Yu et al., 2006; Akter et al., 2008), the low power of 2/3 prescaler is proposed using a 0.18 μm CMOS technology. Compared with the existing design during that time, a 25% reduction of power consumption is achieved and maximum operating frequency up to 4 GHz. These shows that TSPC can be achieve the low power consumption. However, the operating frequency still not wide band and need to be improve. Zhiming Deng et al. as in (Deng and Niknejad, 2010) has improve this disadvantage by using 65 nm LP CMOS technology shows that the maximal input frequencies can be 19 GHz and 16 GHz for divide-by2 and divide-by-2/3 prescaler respectively, and the power consumption is less than 0.5 mW. The TSPC technique for the frequency divider also can be improved in term of speed of to operate the frequencies. In (Chen et al., 2011), Wu-Hsin Chen et al. has implemented in a 130 nm technology and at same process condition, the maximum speed of the 2/3 prescaler reaches 88% of the maximum operating frequency of a single TSPC flip-flop. The maximum operating range that achieved is 3.4 – 5 GHz. However, the power