Design and Realization of FIR Filter for Inter Satellite Link at 50-90 MHZ Frequency using FPGA Desain dan Realisasi Filter FIR untuk Inter Satellite Link pada frekuensi 50-90 MHz menggunakan FPGA Yuyu Wahyu *,a , Ken Paramayudha a , Lutfi Jamil Setiawan b , Heroe Wijanto b , M. Shiddiq S. H. c a Pusat Penelitian Elektronika dan Telekomunikasi, Lembaga Ilmu Pengetahuan Indonesia. Komp LIPI Gd 20, Jl. Sangkuriang 21/54D, Bandung 40135, Indonesia b Program Studi Teknik Telekomunikasi, FakultasTeknik, Universitas Telkom Bandung, Indonesia c Sekolah Teknik Elektro dan Informatika, Institut Teknologi Bandung. Labtek VIII, Jalan Ganesha No. 10, Bandung 40132, Indonesia Abstract In this paper, design and realization of FIR filter with a bandwidth of 40 MHz at 50-90 MHz frequency has been proposed. The design was destined to be implemented on the Inter Satellite Links (ISL). This kind of filter had been selected due to a need in linear phase responseon the ISL data communication. Equiripple method was used to design the filter becauseof its reliability in minimizing the magnitude errors. The design of this FIR filter was conducted with theoretical calculation and simulation using the R2012b Matlab. For the implementation, FPGA was used with a VHDL as the programming language with a help of Xilinx ISE Design Suite 14.5. Simulation results in Matlab and Simulink indicated that the filter design could be well implemented on ISL at frequency of 50 MHz - 90 MHz with stopband of 60 db. The phase responseresult of the realized design is quite linear so that the filter is suitable for data communication on the ISL. Keywords : FIR filter, equiripple, FPGA, VHDL. Abstrak Dalam tulisan ini, desain dan realisasi filter FIR dengan bandwidth 40 MHz pada frekuensi 50 - 90 MHz telah dibuat. Desain dimaksudkan untuk diterapkan pada Inter Satellite Link (ISL). Jenis filter FIR dipilih karena kebutuhan dalam respon fase linier pada komunikasi data ISL. Metode Equiripple digunakan untuk merancang filter karena kehandalan dalam meminimalisasi kesalahan. Metodologi desain filter FIR ini dimulai dengan perhitungan teoritis dan simulasi menggunakan R2012b Matlab. Untuk realisasinya, FPGA digunakan dengan VHDL sebagai bahasa pemrograman dan dengan bantuan software Xilinx ISE Design Suite 14,5. Hasil simulasi di Matlab dan Simulink menunjukkan bahwa desain filter dapat diimplementasikan pada ISL pada frekuensi 50 MHz - 90 MHz dengan stopband sebesar 60 db. Hasil respon fase pada realisasi cukup linear sehingga filter cocok digunakan untuk komunikasi data pada ISL. Kata kunci : Filter FIR, equiripple, FPGA, VHDL. I. INTRODUCTION The satellite is an object that orbits around the earth that is normally used by humans as to communicated, weather monitoring, etc. The satellite technology continues to evolve. An Inter satellite links (ISL) is one of the technology that can make the satellites connect directly with other satellites. The ISL is a solution of the existing problems on LEO satellites monitoring the earth. These satellites can only send a picture when the position above the earth station which causes the delay to get information. Therefore, the earth stations is made with large numbers in order to continue monitoring the LEO satellite. However, this requires a considerable high cost. Because of that the ISL which can communicate the satellites directly with other satellites assessed more quickly and efficiently. Filter is one of the components used in the ISL. The filter is used to pass the signals by passing frequency digital signal which contains the required info and reduce the undesired signal. In the recent years, many research of Finite Impulse Response (FIR) filters had been conducted. Some applications that could be implemented using this kind of filters are: image sampling [1], image coding [2], beamforming [3], software radio [4], audio [5], hearing aid [6] and DSP application [7] In this paper, design and realization of FIR Filter with bandwidth of 40 MHz at 50-90 MHz frequency for ISL application are done. An Equiripple method was used to design the filter because of its reliability in minimizing the magnitude errors. The design of this FIR filter was conducted with theoretical calculations and simulated using Matlab R2012b. For the implementation, FPGA was used with VHDL as the * Corresponding Author. Email: yuyuwahyusr@gmail.com Received: November 22, 2016; Revised: November 30, 2016 Accepted: December 2, 2016 Published: December 15, 2016  2016 PPET - LIPI doi: 10.14203/jet.v16.15-19