Accelerated Publication Memristor structures for high scalability: Non-linear and symmetric devices utilizing fabrication friendly materials and processes Janice H. Nickel a,⇑ , John Paul Strachan a , Matthew D. Pickett a , C. Tom Schamp b , J. Joshua Yang a , John A. Graham c , R. Stanley Williams a a Hewlett-Packard Laboratories, 1501 Page Mill Rd., Palo Alto, CA 94304, United States b SVTC Technologies, 2706 Montopolis Drive Austin, TX 78741, United States c Graham Technology Consulting, LLC, Fort Collins, CO 80525, United States article info Article history: Received 9 August 2012 Received in revised form 14 September 2012 Accepted 24 September 2012 Available online 2 October 2012 Keywords: Crossbar Fabrication Memristor Memory abstract Non-linear, bipolar memristor crossbar structures, suitable for high scalability, have been fabricated in fully compatible Back-End-of-Line materials and processes. The original four mask fabricated crossbar structure exhibited poor electrical characteristics. Detailed failure analysis revealed significant process- ing artifacts affecting device behavior, including leakage currents from sidewall conduction and thicker than anticipated switching layer. To resolve the problems created by these processing artifacts, a novel device structure, termed ‘‘reverse dual damascene’’, was designed and implemented. We present device and failure analysis results from the original structure, the revised structure and process, and show the improved device electrical characterization results. Ó 2012 Elsevier B.V. All rights reserved. 1. Introduction Memristors show great promise for memory applications due to their scalability, reliability, and compatibility with Back- End-of-Line (BEOL) fabrication processes [1]. Results published in the literature have generally been on laboratory made devices of- ten utilizing Pt electrodes and unpatterned blanket oxide materials [2–4], [11]. For widespread adoption, Resistive Random Access Memory (RRAM) requires industry standard fabrication processes and materials. Recently, standard Front End fabrication techniques have been used in the linear HfO x [5] and Transition Metal Oxide (TMO) [12] systems, but these material sets do not permit high scalability since they require transistors as select devices. Results of RRAM integrated with Complementary Metal Oxide Structures (CMOS) utilizing linear RRAM elements also require the incorpora- tion of a significant number of transistors to avoid leakage paths [13]. In contrast, bilayer, bipolar memristor devices can exhibit high non-linearity [6] in their current–voltage relationship. Device non- linearity acts as an effective selection device, removing the require- ment of utilizing CMOS circuitry for selection and reduction of sneak currents – enabling stacking of true 4F 2 crossbar structures. The ability to stack multiple layers of true crossbar structures will enable scalability to continue well into the future. To minimize mask steps, it is preferable to share conductors between successive crossbar planes. Sharing conductors requires either a symmetrical output from the device, or multiple sense circuitries to accommo- date an asymmetrical device output. Combining non-linearity and symmetrical output is an optimal scenario to obtaining extreme scalability well beyond 4F 2 [7]. We report results on non-linear, symmetric, memristor crossbar devices, utilizing a novel RRAM device structure, fabricated in stan- dard BEOL materials and processes at Novati Technologies, Inc.’s 300 mm wafer line. 2. Initial structure 2.1. Simple crossbar structure fabrication Non-linear bilayer, bipolar memristors were initially fabricated using a four mask process to define Bottom Conductors (BC), memristor stacks, via and Top Conductors (TC) utilizing the 130 nm critical dimension node. Fig. 1(a)–(d) depicts the process used. A Cu damascene bottom conductor (Fig. 1(a); mask step 1) was followed by the blanket deposition of the memristor stack (Fig. 1(b)) composed of TaN [10 nm]/TiN [15 nm]/TiO 2x [35 nm]/ TiO 2 [4 nm]/TiN [15 nm]/TaN [10 nm]. TaN is a diffusion barrier (prevents Cu migration); TiN forms the Bottom Electrode (BE) and Top Electrode (TE); TiO 2x is a vacancy reservoir [8] as well as the non-linear element [6]; and TiO 2 is the active switching layer. TiN and TiO 2 were reactively sputtered from a Ti target 0167-9317/$ - see front matter Ó 2012 Elsevier B.V. All rights reserved. http://dx.doi.org/10.1016/j.mee.2012.09.007 ⇑ Corresponding author. Tel.: +1 650 857 5299; fax: +1 650 813 3312. E-mail address: Janice.Nickel@hp.com (J.H. Nickel). Microelectronic Engineering 103 (2013) 66–69 Contents lists available at SciVerse ScienceDirect Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee