National Conference on Modeling & Simulation of Electrical Systems [MSES-2013], TIT & S, Bhopal 170 A New Approach for Locking PLL Using AMS Simulation M. Jagath Vallabhai Pavan Mehta Dept.of Electrical & Electronics Dept.of Electrical & Electronics MANNIT, Bhopal TIT College,Bhopal(M.P.) pawan71983@gmail.com Abstract – The phase locked loop (PLL) is primary requirement for the synchronous communication system, because the clock synchronization is must for proper data receptions. In such systems the synchronization is performed by PLL. This paper presents a new design for the fast locking digital PLL which reduced the locking time greatly. The paper also presents the simulated results of the proposed DPLL in mixed signal environment by using VHDL-AMS. The VHDL-AMS is used here because of simplicity & its capability to perform the simulation of systems that contains both analog and digital components. Finally the simulation result shows that the proposed model performs well. Keywords – Digital Phase Locked Loop, VHDL-AMS, and Phase Frequency Detector. I. INTRODUCTION The basic work of a PLL is to track the frequency & to synchronize the local clock with given clock. Phase-locked loops are widely employed in radio, telecommunications, computers and other electronic applications. They can be used to recover a signal from a noisy communication channel, generate stable frequencies at a multiple of an input frequency (frequency synthesis), or distribute clock timing pulses in digital logic designs such as microprocessors. Since a single integrated circuit can provide a complete phase-locked-loop building block, the technique is widely used in modern electronic devices, with output frequencies from a fraction of a hertz up to many gigahertz’s. In present scenario of digital systems a new type of PLL issued which are called Digital PLL and defined as type of PLL used to synchronize digital signals. While DPLLs input and outputs are typically all digital, they do have internal functions which are dependent on analog signals. There are many digital PLL topologies have been already proposed by many authors using different enhancement in A different part of the systems. In our approach we modified the charge pump section and made it non linear tracking fast changing signals quickly. The approach is inspired by the method proposed by the Dr. Mahmoud FawzyWagdy [1] et. al. they used some frequency comparators for quickly changing the response of loop filter we have taken the same topology for all other units as taken by them and given in [2]. The rest of the paper arranged as follows the second section presents a basic review on working of digital PLL with the components used then nextSection presents the proposed topology followed by simulation results and conclusion in next two sections. II. DIGITAL PLL Digital PLLs are a type of PLL used to synchronize digital signals. While DPLLs input and outputs are typically all digital, they do have internal functions which are dependent on analog signals. There are four basic components of a DPLL [3]. • Phase Detector • Loop Filter • Voltage Controlled Oscillator (VCO) • Divider The block diagram of the basic digital PLL is shown in Figure 1. Phase Detector: the work of this section is to compare the phase of the input clock with VCO clock and produce the output respectively generally two types of phase detectors are used, an XOR gate and a phase frequency detector (PFD), both have significantly different characteristics. A. XOR Phase Detector This is a two input XOR gate and it utilizes the property of XOR gate. Since the XOR produces the logic high whenever it detects the non similar inputs and that can be seen as the phase difference between two inputs. The behavior of XOR phase detector is defined below: