MODELING OF METAL-OXIDE-SEMICONDUCTOR CAPACITOR ON INDIUM GALLIUM NITRIDE 1- CHANNEL MODEL Tarik Menkad 1 , student member, IEEE, Dimiter Alexandrov 1,2 , and Kenneth Scott A. Butcher 1,2 1 Semiconductor Laboratory, Department of Electrical Engineering, Lakehead University, 955 Oliver Rd, Thunder Bay P7B 5E1, Ontario, Canada. 2 Meaglow Ltd, 1294 Balmoral St, Suite 150, Thunder Bay P7B 5Z5, Ontario, Canada ABSTRACT A new analytical model for a two terminal metal-oxide- Gallium Nitride/Indium Gallium Nitride heterojunction structure is presented. This model characterizes the space charge layer created by electron tunneling in the structure’s channel which is made of intrinsic Gallium Nitride. A one dimensional (1-D) analysis is adopted, and a set of hypotheses is stated to frame the present work. Index Terms— Gallium Nitride GaN, Indium Gallium Nitride In 0.5 Ga 0.5 N, excitons. 1. INTRODUCTION Excitons found in In x Ga 1-x N alloy are used as a basis for the design of a high frequency field effect transistor [1]. This transistor uses excitons as a quantum source of free electrons for its channel made of intrinsic Gallium Nitride. Electrons, under the influence of an external electric field, move in an intrinsic material and experience reduced scattering. The high mobility in the channel allows low-noise and high-speed performance. The metal- oxide- semiconductor on In 0.5 Ga 0.5 N capacitor, which forms the core of this high-frequency field-effect transistor, is the subject of the present work. Quasi-static C-V characteristic are obtained. For this purpose, a set of hypotheses are stated in order to set the scope and the domain for the validity of this model. Channel conductivity is modulated by the value of the free electric charge present in the intrinsic GaN material. This charge is due to electrons of excitons origin, which tunnel through the i-GaN/p-In 0.5 Ga 0.5 N heterojunction. The determination of the charge density distribution, the electric field through the channel thickness, and the potential drop across the channel are essential to relate the electric charge present on the gate to the corresponding applied gate voltage. For this purpose, a channel model is presented. The reader will realize that such a model is a standalone entity and can be introduced separately from the device model, we chose to do it the other way to demonstrate the need for such a channel model in the analysis of the MOS capacitor on In 0.5 Ga 0.5 N. 2. MODEL 2.1. Nomenclature  ࡳࢍ Front gate to back substrate voltage  ଵ ,  ଶ Potential drop across In 0.5 Ga 0.5 N pn junction and across the space-charge layer in p-type In 0.5 Ga 0.5 N side of the i-GaN/p-In 0.5 Ga 0.5 N heterojunction  ଷ ,  ସ Potential drop across i-GaN, oxide layers ݐ ௢௫ ݐ, ௔ே Oxide and GaN layers thicknesses.   ᇱ , ௔ே ᇱ Charge per unit area on the gate, in GaN layer  ௣ூ௡ బ.ఱ ௔ బ.ఱ ே ᇱ Charge per unit area in space charge region located in p-type In 0.5 Ga 0.5 N side of the i-GaN/p-In 0.5 Ga 0.5 N heterojunction.  ௖௛ Free electron concentration present in intrinsic Gallium Nitride layer. ܨ ଴ Electric field in GaN layer at the i-GaN/p- In 0.5 Ga 0.5 N heterojunction.  ௣௢ , ௣௢ Thermal equilibrium hole and electron concentrations in p-In 0.5 Ga 0.5 N. ߝ ௢௫ ߝ, ௔ே Relative permittivity of oxide and GaN ߝ ூ௡ బ.ఱ ௔ బ.ఱ ே ߝ, ௢ Relative permittivity of In 0.5 Ga 0.5 N, and permittivity of vacuum. ݑ  Thermal voltage q Elementary charge 2.2. Set of hypotheses 1) Consider a 1-D dimension model. 2) The oxide material is considered an ideal insulator, no trapped charges exist. 3) The GaN surface at the interface oxide/GaN is considered to be ideal, with no defects or traps or recombination centers near the surface. 4) All semiconductors are considered to be non degenerate, so that Boltzmann statistics can be used. 5) No temperature gradient is present. The device dimensions are small enough, that we assume that heat distributes evenly throughout the device. 6) Polarization is not considered; so that displacement and electric vector fields are directly proportional. 2012 25th IEEE Canadian Conference on Electrical and Computer Engineering (CCECE) 978-1-4673-1433-6/12/$31.00 ©2012 IEEE