Introductory invited paper On the time-dependent degradation of LDD n-MOSFETs under hot-carrier stress D.S. Ang, C.H. Ling* Faculty of Engineering, The National University of Singapore, 10 Kent Ridge Crescent, Singapore 119260 Received 21 May 1999 Abstract A uni®ed model for hot-carrier-induced degradation in LDD n-MOSFETs is presented. A novel oxide spacer charge pumping method enables interface trap generation in the spacer and overlap/channel regions to be distinctly separated. An excellent correlation between trap generation in the spacer region and linear drain current degradation at high gate voltage is observed. Moreover, trap generation in the overlap/channel region is found to correlate well with linear drain current degradation at low gate voltage. The results point unambiguously to a two- mechanism degradation model involving drain resistance increase by trap generation in the spacer region, and carrier mobility reduction by trap generation in the overlap/channel region. The combined eect of a time- independent lateral electron temperature pro®le and a ®nite density of interface trap precursors within the LDD region leads to a self-limiting degradation behavior. This insight forms the basis of a time-dependent trap generation model, which indicates the existence of a single degradation curve. The fact that the degradation curves at dierent stress drain voltages fall onto a time-scaled version of the single degradation curve provides strong support for the model. This also oers a straightforward and yet accurate means by which the hot-carrier lifetime corresponding to a speci®c failure criterion may be extracted. Finally, a power-law relationship between hot-carrier lifetime and substrate current is also observed for the LDD devices, thus preserving the physical essence based on which earlier lifetime models for conventional drain devices are established. # 1999 Elsevier Science Ltd. All rights reserved. 1. Introduction Hot-carrier-induced degradation has been recognized as one of the most important reliability problems limit- ing the downscaling of metal-oxide-semiconductor ®eld-eect transistors (MOSFETs) [1]. The past two decades have witnessed extensive interests in this ®eld, with a common objective of understanding the basic mechanisms involved [2±9], and prolonging the oper- ational lifetime of devices through novel modi®cations of the basic MOSFET structure [10±15]. One approach, which has achieved much success, is the lightly doped drain (LDD) structure [10,11]. However, the LDD structure introduces parasitic series resistance which degrades device performance [16,17]. Throughout the years, various improved structures [12±15] have evolved. Among them, the large-angle-tilt implanted drain (LATID) structure [14] has seen wide- spread applications in VLSI/ULSI CMOS technol- ogies. Recently, it has been shown that LDD n-MOSFETs exhibit a dierent degradation behavior [18±24] com- pared to their conventional-drain counterparts [4,6]. It has been well established, for the latter, that the time- dependent degradation of parameters such as linear Microelectronics Reliability 39 (1999) 1311±1322 0026-2714/99/$ - see front matter # 1999 Elsevier Science Ltd. All rights reserved. PII: S0026-2714(99)00053-0 www.elsevier.com/locate/microrel * Corresponding author. Tel.: +65-874-2128; fax: +65-779- 1103. E-mail address: eleling@nus.edu.sg (C.H. Ling)