Plasma Process-Induced Latent Damage on Gate Oxide zyx ---- Demonstrated by Single-layer and Multi-layer Antenna Structures zy Zhichun Wang ', Jan Ackaert2, Cora Salm' and Fred Kuper'. ' MESA+ Research Institute / University of Twente, Semiconductor Components Group P.O. Box 2 17,7500 AE Enschede, The Netherlands, Phone: +3 1 53 4892727, Fax: +3 1 53 4891034, E-mail: Z.Wang@,el.utwente.nl Alcatel Microelectronics, Westerring 1 zyxwvu 5, B-9700 Oudenaarde,Belgium 2 3Philips Semiconductors, MOS4YOU, Nijmegen, The Netherlands zyxw Abstract -In this paper, by using both single-layer (SL) and multi-layer (ML) or stacked antenna structures, a simple experimental method is proposed to directly demonstrate the pure plasma process-induced latent damage on gate oxide without any impact of additional defects generated by normal constant current stress (CCS) revealing technique. The presented results show that this method is effective to study the latent damage. 1. Introduction For very-large-scale-integration (VLSI) manufacturing of integrated circuits (ICs), the use of high-density plasma- enhanced deposition and anisotropic etching techniques is required. However, this kind of plasma techniques can cause tunneling currents to flow through thin gate oxides, resulting in charge built-up, generation of new oxide traps and generation of interface states. They cause the loss of the reliability of the metal-oxide-semiconductor (MOS) devices or even the totally failure of the devices [ 11-[3]. The latent damage induced by a plasma process has been identified as an increased number of neutral electron traps and hole traps in the oxide and passivated interface states [4] [SI. It is indicated by electrical properties shifting as function of antenna area or shape after constant current stress (CCS), which is the typical property of plasma process-induced damage (PPID). Recently, many research groups over the world have made a lot of efforts to evaluate the plasma process-induced latent damage zyxwvuts [4] [6]. Normally, a high-field CCS is used to reveal or re-awaken this hidden and inactive damage [7]. However, this high-field CCS also generates additional new defects in the gate oxide simultaneously. In this paper, a simple experimental method is proposed to directly demonstrate the pure latent damage without any impact of additional defects generated by CCS revealing technique. Single-layer (SL) antenna test structures are used to evaluate PPID of each stand-alone plasma process step. And the cumulative PPID of a few plasma processes is evaluated by multi-layer (ML) antenna test structures. The test structure is considered to suffer PPID when there is an antenna present during a certain plasma process. Therefore, the number of layers determines how many plasma process steps are used to introduce damage to the structures. The used SL test structure and ML test structure are described in section 2, and the experimental results are presented and discussed in section 3. The presented experimental data clearly demonstrate the existence of latent damage, since the ML structures that were exposed, but did not fail from antecedent PPID, are more susceptible to subsequent plasma process compared with fresh SL structures that are free from antecedent PPID. 2. Experimental Details In this study, some wafers with SL test structure and ML test structure have been subjected to a 0.35pm CMOS backend-of-line process. After that, the charging sensitive antenna structures [8] of these wafers are evaluated. The gate leakage current (Ilk) failure fraction and the wafer maps of SL and ML antenna structures are compared, and the results are discussed. *. +7 Poly gate -$gm- Protection diode Fig. zyxwvu 1: (a) Schematic layout of metal2 (M2) SL antenna structure with a finger-shaped M2 antenna. A protection 0-7803-6675-1/01/$10.00 zyxwvutsrqp 0 2001 IEEE. 220 Proceedings zyxw of 8''' IPFA 2001, Singapore