0026-2714/$ - see front matter Ó 2005 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2005.07.066 Microelectronics Reliability 45 (2005) 1425–1429 www.elsevier.com/locate/microrel A 3-D Circuit Model to evaluate CDM performance of ICs M.S.B.Sowariraj a , Theo Smedes b Peter C. de Jong b , Cora Salm a , Ton Mouthaan a , Fred G Kuper a,b a University of Twente, P.O.Box 75000, 7500 AE, Enschede, The Netherlands Phone: +31 53 4892729, Fax +31 53 4891034 e-mail: m.s.b.sowariraj@el.utwente.nl b Philips Semiconductors, Gerstweg 2, 6534 AE Nijmegen, The Netherlands. Abstract This paper presents a physical description of the static charge flow through an IC during a CDM event. Based on this description, an equivalent 3-D circuit to model the complete IC under CDM stress is proposed. The model takes into account various factors like package parasitics, substrate resistance, parasitic contacts of the circuit elements with the substrate, bus line resistances, distribution of protection devices. It allows studying the influence of these factors on the voltage transients seen across the gate-oxides of MOS transistors. CDM measurements on an IC with rail based protection showed gate-oxide failure at the MOS transistors in the internal core circuitry. The proposed circuit model is applied to study the voltage transients between the internal MOS transistors gate and local substrate during CDM stress and thereby explain the reason for the observed gate-oxide failure. It is found that V SS line contact distribution with the substrate rail enhances CDM robustness, provided the power lines (V SS and V DD line) are well clamped to each other. 1. Introduction The Charged Device Model (CDM) type of electrostatic discharge (ESD) occurs when a charged IC touches a grounded surface. Thus in this case, the IC is both the source and discharge path for the static charge. CDM stress results in voltage overshoots across the circuit elements. When the voltage drop across the gate-oxide of any MOS transistor exceeds its breakdown threshold voltage level, gate-oxide failure results. With continuous scaling down of device dimensions, especially thinning down of gate- oxides, the vulnerability to CDM gate-oxide failure has increased. For example in a 0.12 μm technology node where the gate-oxide thickness is 3 nm, the gate-oxide breakdown threshold voltage can be ~10 V for 1 ns stress time. The major block to hinder the development of a CDM robust design is the lack of knowledge on the source of discharge current and its path through the circuit during CDM stress. Measurement of internal voltage transients during CDM stress does not give useful information, as the parasitic effects of the additional test set-up would distort the fast transient signals significantly. Failure analysis apart from being very laborious only gives the information about the failure location. Circuit simulations on the other hand can help access the internal nodes. But the reliability of circuit simulation results depends on how accurately the circuit used in the simulation models the actual behavior of the IC during CDM stress. This paper studies the origin of the CDM discharge current and presents an equivalent circuit approach which can model the current and voltage transients across the entire IC during CDM stress. The circuit model is then applied to understand the cause for an Ó 2005 Elsevier Ltd. All rights reserved.