128 Copyright © 2016, IGI Global. Copying or distributing in print or electronic forms without written permission of IGI Global is prohibited. Chapter 6 DOI: 10.4018/978-1-5225-0190-9.ch006 ABSTRACT With the rapidly evolving silicon technology, the power density becomes increasingly high. Quadratically related to power, the voltage scaling ofers a means of minimizing energy. However, power supply scaling demands less threshold voltage, which rises leakage current. Several low power techniques have been devised. This chapter deals with the non-conventional low power design solutions, based on adiabatic switching theory. In such circuits, the energy rather than getting dissipated during every cycle, is trans- ferred back and forth between the logic and power-clock sources. A brief discussion on the reversible logic circuits will be presented followed by the fully adiabatic and quasi-adiabatic circuits. The use of power-clock sources for operating the adiabatic circuits will also be introduced. The generalized energetics of an adiabatic circuit followed by the typical loss models of the adiabatic families are presented. Some of the adiabatic circuits employing CMOS transistors are introduced in the chapter. A short comparison for the adiabatic circuit leakage models follows. INTRODUCTION Need for Low Power With the rapid evolution in silicon technology, the transistor size continues decreasing remarkably, and the chips grow up in functionality with the switching frequencies increasing in parallel. The power dissipation in the chip thus becomes increasingly high. In 1980s, the growing power dissipation in the microprocessors, the memory and a multitude of ASICs prompted an industry-wide shift from the bipo- lar and NMOS technologies to CMOS to assuage the problem of heat dissipation. This attempt greatly reduced the average power dissipation resulting in a provisional solution. However, higher packing Low Power VLSI Circuit Design using Energy Recovery Techniques V. S. Kanchana Bhaaskaran VIT University, India