Genetic Algorithms and Artificial Neural Networks to Combinational Circuit Generation on Reconfigurable Hardware Bruno A. Silva, Mauricio A. Dias, Jorge L. Silva, Fernando S. Osorio Institute of Mathematical Science and Computation (ICMC) Mobile Robotics Lab (LRM) and Reconfigurable Computing Lab (LCR) University of Sao Paulo (USP) Sao Carlos, Brazil {brunoas, macdias, jsilva, fosorio}@icmc.usp.br Abstract—Operating in critical environments is an extremely desired feature for fault-tolerant embedded systems. In addi- tion, due to design test and validation complexity of these sys- tems, faster and easier development methods are needed. Evolv- able Hardware (EHW) is a development technique that, using reconfigurable hardware, builds systems that reconfiguration part is under the control of an Evolutionary Algorithm. Recon- figurable hardware allows EHW to change its own hardware structure adapting itself to task and/or environment changes. Evolvable part of these systems can also be implemented using Artificial Neural Networks (ANNs). This research work presents results and comparisons between Genetic Algorithm (GA) and ANN implementations that receive combinational circuits’ truth-tables as input and searches the minimum circuit respecting this input truth-table. GA improved for this work’s EHW structure achieve good execution time for tested tables and ANN modeling presents some non-desired characteristics with bad results. Keywords-Artificial Neural Network; Evolvable Hardware; Fault-tolerant systems; Embedded Systems; Genetic Algo- rithm; I. I NTRODUCTION Embedded system development refers to important ques- tions: what processing power is needed? Is an operating system necessary? What functionalities the system should have? How amount of memory is needed? Is it a realtime system? Where should be placed hardware accelerators to increase performance? These questions can be answered in an optimized way with help provided by the development environment. Rising complexity of embedded systems originated due to real-time circuits constraints increased the difficulty to find acceptable answers for proposed questions. Consequently, alternatives to simplify projects that also raise circuit’s robustness are becoming important. Researches in last years developed different techniques to design digital circuits and Evolvable Hardware (EHW) is one of them. EHW is a reconfigurable hardware which configuration is under control of an evolutionary algorithm. This hardware allows systems to change their own hard- ware structures in accord to environment or task changes. Moreover, EHW changes project focus: there is no hardware development, the idea is to find a good circuit implementa- tion (genotype) and a specification project to evaluate circuit functionalities (fitness). FPGA’s (Field Programmable Gate Arrays) are one of the most used hardware to implement EHW. FPGA’s are reconfigurable devices with high flexibility for digital circuit design, test and validation. Nowadays, FPGA manufacturers, as Xilinx and Altera Corporation, also develop integrate development environments (IDEs) for rapid and low-cost complex embedded system developments. There are many ways to optimize circuits using their truth- table representation. For this purpose, heuristic algorithms have been developed and used. Some examples are the ESPRESSO algorithm [12] and Genetic Algorithms (GA’s). Another possibility to project digital circuits is using Artifi- cial Neural Networks (ANN’s) to optimize truth-tables. ESPRESSO algorithm is an heuristic method that is very fast and give solutions near to exact minimum. The Genetic Algorithm (GA) was largely diffused in 1989 by Goldberg [4]. In The algorithm executes two basic steps: create an initial population and begin the main loop that evolves this population. The main loop consists of making interactions with individuals (with crossover and mutation operators) and evaluating them, evolving/selecting the best individuals ac- cording to a fitness function. This loop is repeated until reach the stopping criteria. With this procedure, the algorithm is able to keep the best solutions and explore the search space at the same time. Artificial Neural Networks (ANN’s) are structures that make an analogy to human brain’s operation composed by artificial neurons that can be grouped forming networks. These structures can be trained, to solve problems of classifi- cation and pattern recognition for example, using supervised or non-supervised learning algorithms. Supervised learning algorithms need databases that contains inputs and respective expected outputs. The knowledge of ANNs is represented by the value of neurons interconnections weights that are actualized by learning algorithms, usually based on output errors for a given input and expected output pair [13]. The main goal of this work is to verify artificial neural 2010 International Conference on Reconfigurable Computing 978-0-7695-4314-7/10 $26.00 © 2010 IEEE DOI 10.1109/ReConFig.2010.25 179