IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 60, NO. 5, MAY 2012 1365 Two-Way Current-Combining -Band Power Amplifier in 65-nm CMOS Qun Jane Gu, Member, IEEE, Zhiwei Xu, Senior Member, IEEE, and Mau-Chung Frank Chang, Fellow, IEEE Abstract—This paper presents a two-way current-com- bining-based -band power amplifier (PA) in 65-nm CMOS technology. An analytical model and design method for -band power combiners are presented, which indicates current com- bining is preferred for millimeter-wave frequencies due to a good current handling capability, symmetrical design, and low sensitivity to parasitics. To demonstrate the concept, a two-way current-combining-based PA has been fabricated, where each channel utilizes compact and symmetrical transformer-based inter-stage coupling to realize a preferred fully differential implementation. This PA operates from 101 to 117 GHz with maximum power gain of 14.1 dB, saturated output power ( ) of 14.8 dBm, and peak power-added efficiency of 9.4%. The core chip area without pads is 0.106 mm . Index Terms—Power amplifier (PA), power combiner, -band. I. INTRODUCTION T HE -band of the electromagnetic (EM) spectrum is promising for various applications such as wireless sensing, imaging, and communications. Its unique charac- teristic of penetration through fog/rain/cloud could enable all-weather radar and sensing. The wide bandwidth around this frequency also makes it very attractive to ultrahigh-speed wireless and satellite communications [1]–[3]. In these -band systems, power amplifiers (PAs) are one of the most challenging components because of the requirements of high output power and energy efficiency. Conventionally, -band amplifiers are mainly based upon discrete III–V compound semiconductor de- vices [4], [5]. However, current III–V semiconductor processes are not suitable to support very large scale integrated (VLSI) digital circuits, which is indispensable for system-on-a-chip (SoC). Therefore, multichip integration becomes necessary, and tends to produce a large form factor system. The associated inter-chip integration also introduces the complicated interface circuitries among different chips. Manuscript received October 01, 2011; revised January 06, 2012; accepted January 10, 2012. Date of publication March 08, 2012; date of current version April 27, 2012. This paper is an expanded paper from the IEEE RFIC Sympo- sium, June 5–10, 2011, Baltimore, MD. Q. J. Gu is with the Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL 32608 USA (e-mail: qgu@ece.ufl.edu). Z. Xu is with HRL Laboratories LLC, Malibu, CA 90265 USA. M.-C. F. Chang is with the Electrical Engineering Department, University of California at Los Angeles, Los Angeles, CA 90095 USA (e-mail: mfchang@ee. ucla.edu). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2012.2187536 On the other hand, silicon processes, especially CMOS technologies, have the advantages of high level integration, small form factor, and potential low cost. Therefore, CMOS millimeter-wave circuits have the potential to materialize wide deployment, and thus attract lots of research interest [6]–[11]. In millimeter-wave PA research, -band (50–75 GHz) CMOS PAs have been demonstrated to deliver up to 20-dBm satu- rated output power with 20% power-added efficiency (PAE) [12]–[19]. Recent -band CMOS PA studies have also demon- strated higher than 10-dBm with power efficiencies less than 6% [20], [21]. To further increases output power and efficiency of -band CMOS PAs, the inherent drawbacks of silicon processes must be overcome. First, the existing CMOS device speed is still limited. For instance, and of the devices in 65-nm CMOS technology are around 200 GHz. It does not provide suf- ficient margin to process -band frequency signals. Therefore, switch-mode PAs, potentially with higher efficiency, are not applicable due to the required high-order harmonic operations. It suggests a linear PA approach at the cost of low efficiency. Second, silicon processes inherent high losses degrade PA efficiency. The losses include silicon substrate coupling losses, interconnect electrical and magnetic coupling losses, and con- tact ohmic losses. Such a drawback mandates optimization of both active and passive devices for high-frequency PAs. Third, low supply and breakdown voltages in deep-submicrometer CMOS technologies constrain high power delivery. Reducing output impedance can increase output power, but at the cost of low efficiency due to higher losses from the impedance matching network with a higher impedance transformation ratio. Consequently, such optimization leads to tradeoffs be- tween output power and efficiency. To mitigate this issue, power-combining structures with multiple PA channels are widely adopted [14]–[20]. Three power-combining schemes are normally used in millimeter-wave PAs: direct current com- bining, Wilkinson power combining, and transformer-based power combining. Each scheme has its own pros and cons and will be discussed in Section II. After a detailed comparison among existing power com- biners, we conclude that transformer-based current combiners are more suitable for ultrahigh-frequency operations. Hence, he demonstrate a two-way current-combining -band PA in a 65-nm CMOS technology. Section II describes the design in detail, including the CMOS PA challenges, comparisons of power combiners, advantages of current combiners and the associated designs, and the optimization of each channel PA. Section III presents measurement results, and is then followed by a conclusion in Section IV. 0018-9480/$31.00 © 2012 IEEE