Mitsubishi Electric Research Laboratories
Cambridge Research Center
Technical Report 94-17 September 30, 1994
A General Purpose Queue
Architecture for an ATM Switch
Hugh C. Lauer
Abhijit Ghosh
Chia Shen
Abstract
This paper describes a general purpose queue architecture for an ATM switch capable of support-
ing both real-time and non-real-time communication. The central part of the architecture is a kind
of searchable, self-timed FIFO circuit into which are merged the queues of all virtual channels in
the switch. Arriving cells are tagged with numerical values indicating the priorities, deadlines, or
other characterizations of the order of transmission, then they are inserted into the queue. Entries
are selected from the queue both by destination and by tag, with the earliest entry being selected
from among a set of equals. By this means, the switch can schedule virtual channels indepen-
dently, but without maintaining separate queues for each one. This architecture supports a broad
class of scheduling algorithms at ATM speeds, so that guaranteed qualities of service can be
provided to real-time applications. It is programmable because the tag calculations are done in
microprocessors at the interface to each physical link connected to the switch.
Presented at Massachusetts Telecommunications Conference,
University of Massachusetts at Lowell, Lowell, MA, October 25,1994.
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