International Journal of Advancements in Technology http://ijict.org/ ISSN 0976-4860 Vol 2, No 2 (April 2011) ©IJoAT 285 Dynamic Partial Reconfiguration of FPGA for SEU Mitigation and Area Efficiency Vijay G. Savani, Akash I. Mecwan , N. P. Gajjar Institute of Technology, Nirma University vijay.savani@nirmauni.ac.in , akash.mecwan@nirmauni.ac.in , nagendra.gajjar@nirmauni.ac.in Abstract The fast growing VLSI industry demands new techniques for configuring the FPGA. When it comes to defence and space application the configuration of the FPGA becomes more crucial. When it is required to configure the FPGA automatically, the need arises of more sophisticated and fast techniques for reconfiguration of FPGA. In the space application, the effect of radiation changes the bit patterns in the SRAM cells of FPGA, so it is required to put FPGA into its original condition before SEU. Considering all the facts the paper discusses the mitigation techniques for Single Event Upset (SEU) through Dynamic Partial Reconfiguration of FPGA. It is also very useful to save area of the FPGA by reconfiguration. For the proof of concept up and down sampler are developed as a reconfiguration module and then used for Dynamic Partial Reconfiguration technique. The timing and area requirement of reconfiguration using various techniques is the major focus of the paper. Keywords: Single Event Upset (SEU), Reconfiguration, Mitigation. 1. Introduction In the modern era the FPGAs are widely use to make the prototype of any system. In the space application FPGAs are more used because the designing with FPGA is easy and fast. Many times it is also required to reprogram the chip. FPGA is very flexible to reprogram. Xilinx Virtex FPGAs offer to exploit the features of dynamic and partial run-time reconfiguration. One of the major motivations of this paper is to give the proof of concept of DPR to mitigate the soft-errors in FPGA designs when we use it for space application. Single event upset (SEU) is defined by NASA as "Radiation-induced errors in microelectronic circuits caused when charged particles (usually from the radiation belts or from cosmic rays) lose energy by ionizing the medium through which they pass, leaving behind a wake of electron hole pairs" [10]. SEUs are soft errors, and are nondestructive. An SEU may occur in analogue, digital, optical components, or may have effects in surrounding interface circuitry. FPGAs based on SRAM can be reprogrammed an unlimited number of times, even in the end-user system. The Single Event Upset occurs when radiation affects the transistors that are part of the look up table logic of the FPGA. If the lookup table is affected by radiation can change the bit values associated with the hardware made up of the current FPGA design. SEU is a change of state caused by ions or electro-magnetic radiation striking a sensitive node (area) in a micro- electronic device (Bit-Flip) as shown in the figure 1. The state change is a result of the free charge created by ionization in or close to an important node of a logic element. In these FPGAs, a multitude of latches, also called memory cells or RAM bits, define all logic functions and on-chip interconnects. Such latches are similar to the 6- transistor storage cells used in SRAMs, which has proved to be sensitive to single event upsets caused by high- energy neutrons [11].