Sub-1 V supply 5 nW 11 ppm/°C resistorless sub-bandgap voltage reference Oscar E. Mattia 1,2 • Hamilton Klimach 3 • Sergio Bampi 4 Received: 30 September 2014 / Revised: 23 March 2015 / Accepted: 13 June 2015 Ó Springer Science+Business Media New York 2015 Abstract In this work a resistorless sub-bandgap voltage reference topology is presented. It is a self-biased and small area circuit that works in the nano-ampere con- sumption range, and under 1 V of power supply. The behavior of the circuit is analytically described, a design methodology is proposed and simulation results are pre- sented for two CMOS processes, XFAB 0.18 lm and IBM 0.13 lm. Experimental results from one fabrication run demonstrate a reference voltage of 570 mV, with a tem- perature coefficient as low as 11 ppm/°C for the 0–125 °C range, while the power consumption of the whole circuit is 5 nW under a 0.9 V supply at 27 °C. The occupied silicon area is 0.0022 mm 2 . Keywords Analog CMOS  Bandgap reference  Resistorless  Low-voltage  Low-power 1 Introduction Voltage references are fundamental circuit blocks, ubiq- uitously used in analog, mixed-signal, RF and digital sys- tems, including memories. Basically, their structure can be divided into three fundamental functions: the generation of two voltages (or currents), one proportional and the other complementary to absolute temperature (PTAT and CTAT, respectively) and biasing. The biasing function is some- times implemented together with the PTAT generator, reducing area and complexity, as done in the classical bandgap reference (BGR), introduced by Widlar in 1971 [14]. Traditionally in BGR circuits the CTAT voltage is implemented with a p-n junction, which presents a slightly non-linear behavior over temperature [11]. This non-lin- earity is the main contributor to the curvature over tem- perature usually seen in such circuits, and it directly impacts the temperature coefficient (TC) of the reference voltage. If a TC under 10 ppm/°C is to be achieved, resistorless BGRs must either operate under a limited temperature range [6] or implement a curvature compen- sation technique [8]. Even though vertical parasitic BJTs allow the design of BGR circuits in CMOS technologies, many of the most recent developments in resistorless voltage references have used the MOSFET threshold voltage to implement the CTAT function [2, 3, 10, 12]. These references achieve lower supply voltages, TCs and current consumption with respect to their BJT counterparts, but most of them present variability issues due to high process spread of the threshold voltage. In this paper we propose a self-biased and small area sub-BGR topology, working in the nano-ampere current consumption range and under 1 V of power supply. The & Oscar E. Mattia oscar.mattia@gmail.com; oscar.elisio.mattia@imec.be Hamilton Klimach hamilton.klimach@ufrgs.br Sergio Bampi bampi@inf.ufrgs.br 1 Microelectronics Graduate Program, Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil 2 Present Address: mmWave Group, imec, Kapeldreef, 75, 3001 Heverlee, Belgium 3 Electrical Engineering Department, Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil 4 Informatics Institute, Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil 123 Analog Integr Circ Sig Process DOI 10.1007/s10470-015-0582-3