INTEGRATION, the VLSI journal 26 (1998) 117 — 140 FTROM: A Silicon Compiler for Fault-tolerant ROMs Anurag Gupta*, Kanad Chakraborty, Pinaki Mazumder  Intel Corporation, 2200 Mission College Blvd., Santa Clara, CA 95052—8119, USA  IBM Microelectronics, E. Fishkill, 1580 Route 52, Hopewell Junction, NY 12533—6531, USA  Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, MI 48109—2122, USA Abstract This paper describes a new CAD tool, FTROM — Fault-Tolerant ROM compiler, which synthesizes layout geometries of fault-tolerant ROM modules with flexible, user-specified geometry and CMOS design-rule parameters. This physical design tool produces high-quality built-in self-testable (BIST) and fault-tolerant ROM layouts and uses a novel, minimum-delay overhead approach for fault-tolerance. A tool like FTROMeliminates the high cost of external testing of embedded ROM macros with I/O pins that are difficult to control and observe.  1998 Published by Elsevier Science B.V. All rights reserved. Keywords: Built-in self-test (BIST); Built-in self-repair (BISR); Fault-tolerance; Read only memories; Silicon com- pilers 1. Introduction In the eighties and nineties, VLSI physical design and testing have met new challenges and witnessed remarkable growth. As the chip size has grown phenomenally to more than a million- transistors per chip, the complexity of physical design has increased, and more and more sub- circuits have become inaccessible for testing due to the diminishing pin-to-device count. Built-in self-test (BIST) was introduced for various structured logic and memory arrays, to allow compre- hensive testing for functional, electrical and parametric faults. BIST circuits ensure that bad chips will be automatically spotted and eliminated on the production line, thus ensuring quality control. As effective channel lengths of transistors shrink below 0.2 , even minor process variations * Corrresponding author.  Extended version of a paper presented at the IEEE Symposium on Defect and Fault Tolerance in VLSI Systems (Austin, Nov. 1998). This research was partially supported by the Army Research Office under its MURI programs at the University of Michigan and also by the National Science Foundation. 0167-9260/98/$ — see front matter  1998 Published by Elsevier Science B.V. All rights reserved. PII: S 0 1 6 7 - 9 2 6 0 ( 9 8 ) 0 0 0 2 4 - 8