A Robust 130nm-CMOS Built-In Current Sensor Dedicated to RF Applications M. Cimino, H. Lapuyade, M. De Matos, T. Taris, Y. Deval, JB. Bégueret IXL laboratory, Bordeaux, France cimino@ixl.fr Abstract An otherwise well-known ratiometric Built-In Current Sensor (BICS) dedicated to monitor the current of analog and mixed-signal building blocks highlights a dependency with regards to technology discrepancy. In this paper we present a design methodology that allows to dramatically reduce the dependency, yielding to a new version of this BICS. Taking advantage of a 130 nm VLSI CMOS technology, the BICS proposed has a peak-to-peak dispersion lower than 10 % of its output full-scale range. It makes it more suitable to implement the test functionality while maintaining the initial BICS intrinsic performances. The built-in self test methodology is illustrated by monitoring the supply current of a Low-Noise Amplifier (LNA). Measurements confirm the BICS’s low sensitivity to process variations and its transparency relative to the circuit under test (CUT). Index Terms— Design for testability - Built-In current sensor - Analog and mixed-signal integrated circuits - CMOS technology - Robustness. 1 Introduction INCE the first demonstration of the interest of monitoring the current consumption of integrated circuits as a matter of testing [1], a lot of papers have been published on the topic and the technique has been extended to the test of analog and mixed-signal circuit [2, 3]. Concerning the latter an essential advantage is associated to the use of a Built-In Current Sensor (BICS) as it allows for free on-line testing. Nevertheless, such a BICS has to be transparent as analog circuits performances are strongly related to the stability of the voltage biasing. The first transparent sensor has originally been proposed by Maidon et al. [3] and its principle has even proved itself to be efficient in mass production test [4]. The Maidon’s BICS is based upon a sharp use of the parasitic resistor attached to the IC interconnection layers [5, 6]. The most advanced version of this sensor [7] takes advantage of a ratiometric measurement of the current, which allows a linear transfer function whatever the technology dispersion. On the other hand, in this version the absolute value of the transfer function was still strongly related to technology discrepancies, which makes its use in an industrial test procedure quite uneasy. In this paper, we propose a new version of the ratiometric Maidon’s BICS. This version has been specifically designed to be robust in term of dispersions of the absolute transfer function. In addition, the circuit is developed under low voltage constraint induced by the use of a 130nm VLSI CMOS technology which is limited to a 1.2V power supply. A BIST methodology for a LNA is then depicted in order to give an illustration of RF circuit testing. 2 The Maidon’s BICS Principle 2.1 The initial ratiometric BICS The ratiometric Maidon’s BICS was first designed to operate under a 3.3V power supply [7], as the CMOS technology used to implement the circuit was a 0.6μm one. Nowadays, though, deep submicron technologies are available which imposes much lower voltage supply as a consequence of their reduced dimensions. Therefore, the original circuit is not suitable anymore, and the PMOS cascode mirror stage has to be replaced by a classical one, yielding to the topology depicted in Fig. 1. in which an additional current control input, named I pol has also been added in a matter of controlling the overall BICS current consumption. The parasitic metal layer resistors of the initial design have been replaced by simple integrated resistors as they present a low area and a robust design. This topology is able to deal with as low as 1.2V a power supply, as mandated by the 130nm VLSI CMOS technology we are designing the BICS for in this paper. S Proceedings of the Eleventh IEEE European Test Symposium (ETS’06) 0-7695-2566-0/06 $20.00 © 2006 IEEE